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DESCRIPTION
The WM8593 is a high performance multi-channel audio CODEC with flexible input/output selection and digital and analogue volume control. Features include a 24-bit stereo ADC with digital gain control, two 24-bit DACs with independent volume control and clocking, and a range of input/output channel selection options for flexible routing within current and future audio systems. The WM8593 has an eight stereo input selector which accepts input levels up to 2Vrms. One stereo input can be routed to the ADC. All inputs can be routed to an output selector. The output selector inputs two DAC channels and all analogue bypass inputs, and outputs three independent stereo channels at 2Vrms line level. The DAC channels include independent digital volume control, and all three output channels include analogue volume control. The WM8593 is ideal for audio applications requiring high performance and flexible routing options, including flat panel digital TV and DVD recorder. The WM8593 supports up to 2Vrms analogue inputs, 2Vrms outputs, with sample rates from 32kHz to 192kHz on the DACs, and 32kHz to 96kHz on the ADC. The device is controlled via a serial interface with support for 2-wire and 3-wire control with readback. Control of mute, powerdown and reset can also be achieved by pin selection. The WM8593 is available in a 64-lead TQFP package. * * * * * * *
WM8593
24-bit 192kHz 2Vrms Multi-Channel CODEC
FEATURES
* * * * * Multi-channel CODEC with 8 stereo input selector and 3 stereo output selector 4-channel DAC, 2-channel ADC 8x2Vrms stereo input selector with 8x2 channel analogue bypass to output selector 3x2Vrms stereo output selector Audio performance DAC: 100dB SNR typical (`A' weighted @ 48kHz) DAC: -90dB THD typical ADC: 100dB SNR typical (`A' weighted @ 48kHz)
ADC: -90dB THD typical Independent sampling rate for ADC and DACs Independent sampling rate for DAC1 and DAC2 DACs sampling frequency 32kHz - 192kHz ADC sampling frequency 32kHz - 96kHz DAC digital volume control +12dB to -100dB in 0.5dB steps ADC analogue volume control from +30dB to -97dB in 0.5dB steps Output analogue volume control +6dB to -74dB in 0.5dB steps with zero cross or soft ramp to prevent pops and clicks Headphone drive capability on one stereo output with jack detect Digital multiplexer to interface to multiple digital sources - DSP, HDMI, memory card 2-wire and 3-wire serial control interface with readback and hardware reset, mute and powerdown pins Independent master or slave clocking modes Programmable format audio data interface modes I2S, LJ, RJ, DSP 3.3V / 9V Analogue, 3.3V Digital Supply Operation 64-lead TQFP package
* * * * * * *
APPLICATIONS
* * * Digital Flat Panel TV DVD-RW Set Top Boxes
WOLFSON MICROELECTRONICS plc
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Product Preview, January 2007, Rev 1.0 Copyright 2007 Wolfson Microelectronics plc
WM8593 BLOCK DIAGRAM
ADCREFN ADCREFP DACREFN DACREFP DACVMID ADCVMID
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DIO1 MCLK1 BCLK1 LRCLK1 DIO2 MCLK2 BCLK2 LRCLK2 DIO3 MCLK3 BCLK3 LRCLK3 DIO4 MCLK4 BCLK4 LRCLK4 DIO5 MCLK5 BCLK5 LRCLK5 GPIO1 GPIO2
/RESET
MUTE /PWDN MODE /CS SDIN SCLK SDOUT
AGND1
ADC Input Mux
AVDD1
Control Interface
Audio Interface Mux
DVDD DGND AVDD2 AGND2
Volume Control Matrix Channel Selection
Stereo DAC1
Stereo ADC
Volume Control
Digital Filters
Volume Control Matrix Channel Selection
Stereo DAC2
VOUT1L PGA1L VIN1L VIN1R VIN2L VIN2R VIN3L VIN3R VIN4L VIN4R VIN5L VIN5R VIN6L VIN6R VIN7L VIN7R VIN8L VIN8R VOUT1R PGA1R
PGA Input Mux
PGA2L PGA2R
Output Mux
VOUT2L VOUT2R VOUT3L
PGA3L VOUT3R PGA3R
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WM8593 TABLE OF CONTENTS
DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................2 TABLE OF CONTENTS .........................................................................................3 PIN CONFIGURATION...........................................................................................4 PIN DESCRIPTION ................................................................................................5 ABSOLUTE MAXIMUM RATINGS.........................................................................7 RECOMMENDED OPERATING CONDITIONS .....................................................8 SUPPLY CURRENT CONSUMPTION ...................................................................8 ELECTRICAL CHARACTERISTICS ......................................................................8
TERMINOLOGY .......................................................................................................... 10 MASTER CLOCK TIMING ........................................................................................... 11 DIGITAL AUDIO INTERFACE TIMING - SLAVE MODE............................................. 12 DIGITAL AUDIO INTERFACE TIMING - MASTER MODE.......................................... 13 CONTROL INTERFACE TIMING - 2-WIRE MODE .................................................... 14 CONTROL INTERFACE TIMING - 3-WIRE MODE .................................................... 15 POWER ON RESET (POR) ........................................................................................ 16
DEVICE DESCRIPTION.......................................................................................17
INTRODUCTION ......................................................................................................... 17 CONTROL INTERFACE.............................................................................................. 18 2-WIRE (SM-BUS COMPATIBLE) SERIAL CONTROL INTERFACE MODE .............. 18 3-WIRE (SPI COMPATIBLE) SERIAL CONTROL INTERFACE MODE ...................... 20 GLOBAL ENABLE CONTROL..................................................................................... 21 DIGITAL AUDIO INTERFACE ..................................................................................... 21 DIGITAL AUDIO DATA SAMPLING RATES................................................................ 23 DIGITAL AUDIO DATA FORMATS ............................................................................. 25 DAC FEATURES......................................................................................................... 29 ADC FEATURES......................................................................................................... 31 ANALOGUE ROUTING CONTROL............................................................................. 32 DIGITAL ROUTING CONTROL................................................................................... 43 JACK DETECT ............................................................................................................ 54 POP AND CLICK PERFORMANCE ............................................................................ 55
REGISTER MAP...................................................................................................58 DIGITAL FILTER CHARACTERISTICS ...............................................................91 APPLICATIONS INFORMATION .........................................................................94
RECOMMENDED EXTERNAL COMPONENTS .......................................................... 94 RECOMMENDED ANALOGUE LOW PASS FILTER .................................................. 95 EXTENDED INPUT IMPEDANCE CONFIGURATION................................................. 95 EXAMPLE CONFIGURATION FOR JACK DETECT ................................................... 96 RELEVANT APPLICATION NOTES ............................................................................ 96
PACKAGE DIMENSIONS ....................................................................................97 IMPORTANT NOTICE ..........................................................................................98
ADDRESS ................................................................................................................... 98
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WM8593 PIN CONFIGURATION
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ORDERING INFORMATION
ORDER CODE WM8593SEFT/V TEMPERATURE RANGE -25C to +85C PACKAGE 64-lead TQFP (Pb-free) MOISTURE SENSITIVITY LEVEL MSL3 PACKAGE BODY TEMPERATURE 260oC
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WM8593
PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 NAME DIO1 MCLK2 LRCLK2 BCLK2 DIO2 MCLK3 LRCLK3 BCLK3 DIO3 MCLK4 LRCLK4 BCLK4 DIO4 DVDD DGND MCLK5 LRCLK5 BCLK5 DIO5 GPIO1 GPIO2 /PWDN MUTE /RESET AVDD2 AGND2 VOUT3R VOUT3L VOUT2R VOUT2L VOUT1R VOUT1L VIN1L VIN1R VIN2L VIN2R VIN3L VIN3R VIN4L VIN4R VIN5L VIN5R VIN6L VIN6R VIN7L VIN7R VIN8L VIN8R TYPE Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Supply Supply Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input Digital Input Digital Input Supply Supply Analogue Output Analogue Output Analogue Output Analogue Output Analogue Output Analogue Output Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input DESCRIPTION Audio interface port 1 data input/output Audio interface port 2 master clock input/output Audio interface port 2 left/right clock input/output Audio interface port 2 bit clock input/output Audio interface port 2 data input/output Audio interface port 3 master clock input/output Audio interface port 3 left/right clock input/output Audio interface port 3 bit clock input/output Audio interface port 3 data input/output Audio interface port 4 master clock input/output Audio interface port 4 left/right clock input/output Audio interface port 4 bit clock input/output Audio interface port 4 data input/output Digital supply Digital ground Audio interface port 5 master clock input/output Audio interface port 5 left/right clock input/output Audio interface port 5 bit clock input/output Audio interface port 5 data input/output General purpose input/output 1 General purpose input/output 2 Hardware standby mode Hardware DAC mute Hardware reset Analogue 9V supply Analogue ground Output selector channel 3 right output Output selector channel 3 left output Output selector channel 2 right output Output selector channel 2 left output Output selector channel 1 right output Output selector channel 1 left output Input selector channel 1 left input Input selector channel 1 right input Input selector channel 2 left input Input selector channel 2 right input Input selector channel 3 left input Input selector channel 3 right input Input selector channel 4 left input Input selector channel 4 right input Input selector channel 5 left input Input selector channel 5 right input Input selector channel 6 left input Input selector channel 6 right input Input selector channel 7 left input Input selector channel 7 right input Input selector channel 8 left input Input selector channel 8 right input PP Rev 1.0 January 2007 5
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WM8593
PIN 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 NAME ADCREFP ADCVMID ADCREFN DACREFP DACVMID DACREFN AVDD1 AGND1 MODE SDOUT /CS SCLK SDIN MCLK1 LRCLK1 BCLK1 TYPE Analogue Output Analogue Output Analogue Input Analogue Input Analogue Output Analogue Input Supply Supply Digital Input Digital Output Digital Input Digital Input Digital Input Digital Input/Output Digital Input/Output Digital Input/Output Positive reference for ADC Midrail divider decoupling pin for ADC Ground reference for ADC Positive reference for DACs Midrail divider decoupling pin for DACs Ground reference for DACs Analogue 3.3V supply Analogue ground 2-wire/3-wire mode select Serial Data output for 3-wire readback 3-wire serial control interface latch Software mode: serial control interface clock signal Software mode: serial control interface data signal Audio interface port 1 master clock input/output Audio interface port 1 left/right clock input/output Audio interface port 1 bit clock input/output DESCRIPTION
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WM8593
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION Digital supply voltage, DVDD Analogue supply voltage, AVDD1 Analogue supply voltage, AVDD2 Voltage range digital inputs Voltage range analogue inputs Master Clock Frequency Ambient temperature (supplies applied) Storage temperature Pb free package body temperature (reflow 10 seconds) Package body temperature (soldering 2 minutes) Note: 1. Analogue and digital grounds must always be within 0.3V of each other. -55C -65C MIN -0.3V -0.3V -0.3V DGND -0.3V TBD MAX +4.5V +7V +15V DVDD + 0.3V AVDD1 + 2.4V 38.462MHz +125C +150C +260C +183C
THERMAL PERFORMANCE
PARAMETER Thermal resistance - junction to ambient Notes: 1. 2. Figure given for package mounted on 4-layer FR4 according to JESD51-7. (No forced air flow is assumed). Thermal performance figures are estimated. SYMBOL TEST CONDITIONS MIN TYP TBD See note 1 MAX UNIT C/W
RJA
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WM8593 RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital power supply Analogue power supply Analogue power supply Ground Operating temperature range Notes: 1. 2. Digital supply (DVDD) must never be more than 0.3V greater than AVDD1 in normal operation. Digital ground (DGND) and analogue grounds (AGND1, AGND2) must never be more than 0.3V apart. SYMBOL DVDD AVDD1 AVDD2 DGND/AGND1/ AGND2 TA -25 TEST CONDITIONS MIN 2.97 2.97 8.1 TYP 3.3 3.3 9 0 +85 MAX 3.6 3.6 9.9
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UNIT V V V V C
SUPPLY CURRENT CONSUMPTION
PARAMETER Digital supply current Analogue supply current Analogue supply current Standby current SYMBOL IDVDD IAVDD1 IAVDD2 TEST CONDITIONS MIN TYP TBD TBD TBD TBD MAX UNIT mA mA mA A
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD2=9V, AVDD1=DVDD=3.3V, AGND1=AGND2=0V, DGND=0V, TA=+25C, 1kHz signal, fs=48kHz, MCLK=256fs unless otherwise stated
PARAMETER Digital logic levels Input low level Input high level Output low level Output high level Digital input leakage current Digital input capacitance Analogue Reference Levels ADC Midrail Voltage ADC Buffered Positive Reference Voltage DAC Midrail Voltage Potential divider resistance
SYMBOL VIL VIH VOL VOH
TEST CONDITIONS
MIN
TYP
MAX 0.3xDVDD
UNIT V V V V A pF V V V k k
0.7xDVDD 0.1 x DVDD 0.9 x DVDD TBD TBD
ADCVMID ADCREFP DACVMID
AVDD1 to ADCVMID ADCVMID to AGND1 DACVREFP to DACVMID DACVMID to DACVREFN VMID_SEL[1:0] = 01
AVDD1/2 ADCVMID DACREFP/2 100 50 (Note 2)
Analogue Line Outputs Output signal level (0dB) Maximum capacitance load Minimum resistance load Analogue Headphone Outputs Output signal level (0dB) Minimum resistance load Analogue Inputs RL = 32 TBD 16 0.8x AVDD2 / 9 TBD Vrms 1 TBD 2.0x AVDD2 / 9 TBD 11 Vrms nF k
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WM8593
Test Conditions
AVDD2=9V, AVDD1=DVDD=3.3V, AGND1=AGND2=0V, DGND=0V, TA=+25C, 1kHz signal, fs=48kHz, MCLK=256fs unless otherwise stated
PARAMETER Input signal level (0dB) Input impedance Extended input impedance (Note 3) Input capacitance DAC Performance Signal to Noise Ratio1,5
SYMBOL
TEST CONDITIONS
MIN
TYP 2.0 x AVDD1/3.3
MAX TBD 12
UNIT Vrms k k pF dB dB dB dB
10 External resistor = 10k
11 21 TBD
SNR
A-weighted @ fs = 48kHz A-weighted @ fs = 96kHz A-weighted @ fs = 192kHz
TBD
100 100 100
Dynamic Range2,5 Total Harmonic Distortion3,5
DNR THD
A-weighted, -60dB full scale input 1kHz, 0dBFS @ fs = 48kHz 1kHz, 0dBFS @ fs = 96kHz 1kHz, 0dBFS @ fs = 192kHz
TBD
100 -90 -90 -90 100 0.1 0.05 TBD
dB dB dB dB dB Degree dB dB
Channel Separation4,5 Channel Level Matching Channel Phase Deviation Power supply rejection ratio PSRR 1kHz, 100mVpp 20Hz to 20kHz, 100mVpp ADC Performance Signal to Noise Ratio1,5 SNR A-weighted, 0dB gain @ fs = 48kHz A-weighted, 0dB gain @ fs = 96kHz Dynamic Range2,5 Total Harmonic Distortion3,5 DNR THD A-weighted, -60dB full scale input 1kHz, -1dBFS @ fs = 48kHz 1kHz, -1dBFS @ fs = 96kHz Channel Separation4,5 Channel Level Matching Channel Phase Deviation Power Supply Rejection Ratio Analogue Bypass Paths Signal to Noise Ratio1,5 Dynamic Range2,5 Total Harmonic Distortion3,5 Channel Separation4,5 Channel Level Matching Channel Phase Deviation SNR DNR THD A-weighted A-weighted PSRR TBD TBD TBD TBD
50 TBD
100 97 100 -90 -87 100 0.1 0.05 50 TBD 100 100 90 100 0.1 0.05 TBD
dB dB dB dB dB dB dB Degree dB dB dB dB dB dB dB Degree PP Rev 1.0 January 2007 9
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WM8593
Test Conditions
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AVDD2=9V, AVDD1=DVDD=3.3V, AGND1=AGND2=0V, DGND=0V, TA=+25C, 1kHz signal, fs=48kHz, MCLK=256fs unless otherwise stated
PARAMETER Headphone Amplifier Output signal level (0dB) Signal to Noise Ratio
1,5
SYMBOL
TEST CONDITIONS
MIN
TYP 0.8
MAX
UNIT Vrms dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
SNR THD
A-weighted PO=20mW, RL=16 PO=20mW, RL=32
TBD TBD TBD TBD TBD -97 +30 0.5 -100 +12 0.5 -73.5 +6 0.5 TBD
Total Harmonic Distortion Channel Separation4,5 Power Supply Rejection Ratio Digital Volume Control ADC minimum digital volume ADC maximum digital volume ADC volume step size DAC minimum digital volume DAC maximum digital volume DAC volume step size Analogue Volume Control Minimum gain Maximum gain Step size Mute attenuation Crosstalk DAC to ADC
PSRR
1kHz signal, ADC fs=48kHz, DAC fs=44.1kHz 20kHz signal, ADC fs=48kHz, DAC fs=44.1kHz
100
100
dB
ADC to DAC
1kHz signal, ADC fs=48kHz, DAC fs=44.1kHz 20kHz signal, ADC fs=48kHz, DAC fs=44.1kHz
100
dB
100
dB
TERMINOLOGY
1. Signal-to-noise ratio (dBFS) - SNR is the difference in level between a reference full scale output signal and the device output with no signal applied. This ratio is also called idle channel noise. (No Auto-zero or Automute function is employed in achieving these results). Dynamic range (dBFS) - DNR is a measure of the difference in level between the highest and lowest components of a signal. Normally a THD measurement at -60dBFS. The measured signal is then corrected by adding 60dB to the result, e.g. THD @ -60dBFS = -30dB, DNR = 90dB. Total Harmonic Distortion (dBFS) - THD is the difference in level between a reference full scale output signal and the first seven odd harmonics of the output signal. To calculate the ratio, the fundamental frequency of the output signal is notched out and an RMS value of the next seven odd harmonics is calculated. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. All performance measurements carried out with 20kHz low pass filter, and where noted an A-weighted filter. Failure to use such a filter will result in higher THD and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values.
2.
3.
4. 5.
Notes:
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WM8593
1. 2. 3.
All minimum and maximum values are subject to change. This resistance is selectable using VMID_SEL[1:0] - see Figure 51 for full details. See p95 for details of extended input impedance configuration.
MASTER CLOCK TIMING
ADCMCLK/ DACMCLK1/ DACMCLK2 t
MCLKY
Figure 1 MCLK Timing Test Conditions AVDD1, DVDD = 3.3V, AVDD2 = 9V, AGND1, AGND2, DGND = 0V, TA = +25OC PARAMETER Master Clock Timing Information MCLK System clock cycle time MCLK Duty cycle MCLK Period Jitter MCLK Rise/Fall times Table 1 Master Clock Timing Requirements tMCLKY 27 40:60 120 60:40 200 10 ns % ps ns SYMBOL MIN TYP MAX UNIT
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WM8593
DIGITAL AUDIO INTERFACE TIMING - SLAVE MODE
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Figure 2 Slave Mode Digital Audio Data Timing Test Conditions AVDD1, DVDD = 3.3V, AVDD2 = 9V, AGND1, AGND2, DGND = 0V, TA = +25C, Slave Mode, fs = 48kHz, ADCMCLK, DACMCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information ADCBCLK / DACBCLK1 / DACBCLK2 cycle time ADCBCLK / DACBCLK1 / DACBCLK2 pulse width high ADCBCLK / DACBCLK1 / DACBCLK2 pulse width low ADCBCLK / DACBCLK1 / DACBCLK2 rise/fall times ADCLRCLK / DACLRCLK1 / DACLRCLK2 set-up time to ADCBCLK / DACBCLK1 / DACLRCLK2 rising edge ADCLRCLK / DACLRCLK1 / DACLRCLK2 hold time from ADCBCLK / DACBCLK1 / DACBCLK2 rising edge ADCLRCLK / DACLRCLK1 / DACLRCLK2 rise/fall times DIN1/2 hold time from DACBCLK1 / DACBCLK2 rising edge DOUT propagation delay from ADCBCLK falling edge Table 2 Slave Mode Audio Interface Timing tDH tDD 25 4 16 tLRSU tLRH 22 25 5 tBCY tBCH tBCL 80 30 30 5 ns ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
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WM8593
DIGITAL AUDIO INTERFACE TIMING - MASTER MODE
Figure 3 Master Mode Digital Audio Data Timing Test Conditions AVDD1, DVDD = 3.3V, AVDD2 = 9V, AGND1, AGND2, DGND = 0V, TA = +25C, Slave Mode, fs = 48kHz, ADCMCLK, DACMCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information ADCLRCLK / DACLRCLK1 / DACLRCLK2 propagation delay from ADCBCLK / DACBCLK1 / DACLRCLK2 falling edge DOUT propagation delay from ADCBCLK falling edge DIN1 / DIN2 setup time to DACBCLK1 / DACBCLK2 rising edge DIN1 / DIN2 hold time to DACBCLK1 / DACBCLK2 rising edge Table 3 Master Mode Audio Interface Timing tDL 4 16 ns SYMBOL MIN TYP MAX UNIT
tDDA tDST tDHT
4 22 25
16
ns ns ns
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WM8593
CONTROL INTERFACE TIMING - 2-WIRE MODE
t
STHO
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t
DSU
t
STHO
SDIN t
STSU
t
STOP
SCLK t
SCY
t
DH
Figure 4 Control Interface Timing - 2-Wire Serial Control Mode Test Conditions AVDD1, DVDD = 3.3V, AVDD2 = 9V, AGND1, AGND2, DGND = 0V, TA = +25C, Slave Mode, fs = 48kHz, ADCMCLK, DACMCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK pulse cycle time SCLK duty cycle SCLK frequency Hold Time (Start Condition) Setup Time (Start Condition) Data Setup Time SDIN, SCLK Rise Time SDIN, SCLK Fall Time Setup Time (Stop Condition) Data Hold Time Pulse width of spikes that will be suppressed Table 4 Control Interface Timing - 2-Wire Serial Control Mode tSTOP tDHO tps 2 600 900 8 tSTHO tSTSU tDSU 600 600 100 300 300 tSCY 2500 40/60 60/40 400 ns % kHz ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
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WM8593
CONTROL INTERFACE TIMING - 3-WIRE MODE
t CSS /CS t SCLK
SCY
t CSH
t SCS
t
CSS
SDIN t
DSU
LSB t
DHO
SDOUT t
DL
LSB
Figure 5 Control Interface Timing - 3-Wire Serial Control Mode Test Conditions AVDD1, DVDD = 3.3V, AVDD2 = 9V, AGND1, AGND2, DGND = 0V, TA = +25C, Slave Mode, fs = 48kHz, ADCMCLK, DACMCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK rising edge to CSB rising edge SCLK pulse cycle time SCLK duty cycle SDIN to SCLK set-up time SDIN hold time from SCLK rising edge SDOUT propagation delay from SCLK rising edge CSB pulse width high CSB rising/falling to SCLK rising Pulse width of spikes that will be suppressed Table 5 Control Interface Timing - 3-Wire Serial Control Mode tDSU tDHO tDL tCSH tCSS tps 40 40 2 8 tSCS tSCY 80 160 40/60 20 40 5 60/40 ns ns % ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
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WM8593
POWER ON RESET (POR)
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Figure 1 Power Supply Timing Requirements Test Conditions DVDD = 3.3V, AVDD1 = 3.3V, AVDD2 = 9V DGND = AGND1 = AGND2 = 0V, TA = +25oC, TA_max = +125oC, TA_min = -25oC AVDD1max = DVDDmax = 3.63V, AVDD1min = DVDDmim= 2.97V AVDD2max = 9.9V, AVDD2min = 8.1V PARAMETER VDD level to POR defined (DVDD rising) VDD level to POR rising edge (DVDD rising) VDD level to POR falling edge (DVDD falling) VDD level to POR rising edge (AVDD1 rising) VDD level to POR falling edge (AVDD1 falling) VDD level to POR rising edge (AVDD2 rising) VDD level to POR falling edge (AVDD2 falling) Table 6 Power on Reset SYMBOL Vpord Vpord_hi Vpord_lo Vpor1_hi Vpor1_lo Vpor2_hi Vpor2_lo TEST CONDITIONS Measured from DGND Measured from DGND Measured from DGND Measured from DGND Measured from DGND Measured from DGND Measured from DGND MIN 0.27 1.34 1.32 1.65 1.63 1.80 1.76 TYP 0.36 1.88 1.86 1.68 1.65 1.86 1.8 MAX 0.60 2.32 2.30 1.85 1.83 2.04 2.02 UNIT V V V V V V V
Power Supply Input Timing Information
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WM8593
DEVICE DESCRIPTION
INTRODUCTION
The WM8593 is a high performance multi-channel audio CODEC with 2Vrms line level inputs and outputs and flexible analogue and digital input / output switching. The device comprises a 24-bit stereo ADC, two 24-bit stereo DACs with independent sampling rates and digital volume control, a flexible analogue input and output multiplexer and a flexible analogue input and output multiplexer. Analogue inputs and outputs are all at 2Vrms line level, minimising external component count. The DACs can operate from independent left/right clocks, bit clocks and master clocks with independent data inputs. Alternatively, the DACs can be synchronised to use the same clocks with independent data inputs. Each of the DAC audio interfaces can be configured to operate in ether master or slave clocking modes. In master mode, left/right clocks and bit clocks are all outputs. In slave mode, left/right clocks and bit clocks are all inputs. The ADC uses a separate left/right clock, bit clock and master clock, allowing independent recording and playback in audio applications. The ADC audio interface can be configured to operate in either master or slave clocking mode. In master mode, left/right clocks and bit clocks are all outputs. In slave mode, left/right clocks and bit clocks are all inputs. The ADC includes digital gain control, allowing signals to be gained and attenuated between +30dB and -97dB in 0.5dB steps. The DACs include independent digital volume control, which is adjustable between +12dB and -100 dB in 0.5dB steps. The DACs can be configured to output stereo audio data and a range of mono audio options. The input analogue multiplexer accepts eight stereo line level inputs at up to 2Vrms. One stereo input can be routed to the ADC, and all eight stereo inputs can be routed to the output multiplexer. The output analogue multiplexer includes analogue volume control with zero cross, adjustable between +6dB and -73.5dB in 0.5dB steps, and configurable soft ramp rate. Analogue audio is output at 2Vrms line level. The digital audio interface multiplexer allows flexible routing of the digital signals internal to the device between the independent ADC, DAC1 and DAC2 audio interfaces from any of the five digital audio ports. By integrating this functionality into the WM8593, the external component count and board space normally required to switch between various digital audio sources can be significantly reduced. Additionally, a jack detect function is included that allows various paths within the device to be muted when a set of headphones is detected. Control of the internal functionality of the device is by 2-wire or 3-wire serial control interface with readback. The interface may be asynchronous to the audio data interface as control data will be resynchronised to the audio processing internally. In addition, control of mute, power-down and reset may also be achieved by pin control. Operation using system clocks of 128fs, 192fs, 256fs, 384fs, 512fs, 768fs or 1152fs is provided. ADC and DACs may be clocked independently. Sampling rates from 32kHz to 192kHz are supported for both DACs provided the appropriate master clocks are input. Sampling rates from 32kHz to 96kHz are supported for the ADC provided the appropriate master clock is input. The audio data interface supports right justified, left justified, and I2S interface formats along with a highly flexible DSP serial port interface format.
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WM8593
CONTROL INTERFACE
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Control of the WM8593 is achieved by a 2-wire SM-bus-compliant or 3-wire SPI compliant serial interface with readback. Software interface mode is selected using the MODE pin as shown in Table 7 below: MODE Low High INTERFACE FORMAT 2 wire 3 wire
Table 7 Control Interface Mode Selection
2-WIRE (SM-BUS COMPATIBLE) SERIAL CONTROL INTERFACE MODE
Many devices can be controlled by the same bus, and each device has a unique 7-bit address.
REGISTER WRITE
The controller indicates the start of data transfer with a high to low transition on SDIN while SCLK remains high. This indicates that a device address and data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight bits on SDIN (7-bit address and read/write bit, MSB first). If the device address received matches the address of the WM8593, the WM8593 responds by pulling SDIN low on the next clock pulse (ACK). If the address is not recognised, the WM8593 returns to the idle condition and waits for a new start condition with valid address. When the WM8593 has acknowledged a correct address, the controller sends the first byte of control data (B23 to B16, i.e. the WM8593 register address). The WM8593 then acknowledges the first data byte by pulling SDIN low for one SCLK pulse. The controller then sends a second byte of control data (B15 to B8, i.e. the first 8 bits of register data), and the WM8593 acknowledges again by pulling SDIN low for one SCLK pulse. Finally, the controller sends a third byte of control data (B7 to B0, i.e. the final 8 bits of register data), and the WM8593 acknowledges again by pulling SDIN low for one SCLK pulse. The transfer of data is complete when there is a low to high transition on SDIN while SCLK is high. After receiving a complete address and data sequence the WM8593 returns to the idle state and waits for another start condition. If a start or stop condition is detected out of sequence at any point during data transfer (i.e. SDIN changes while SCLK is high), the WM8593 reverts to the idle condition. The WM8593 device address is 34h (0110100) or 36h (0110110), selectable by control of /CS. /CS (PIN 45) 0 1 2-WIRE BUS ADDRESS 34h (0110100) 36h (0110110)
Table 8 2-Wire Control Interface Bus Address Selection
Figure 6 2-Wire Write Protocol
AUTO-INCREMENT REGISTER WRITE
It is possible to write to multiple consecutive registers using the auto-increment feature. When AUTO_INC is set, the register write protocol follows the method shown in Figure 7. As with normal register writes, the controller indicates the start of data transfer with a high to low transition on SDIN while SCLK remains high, and all devices on the bus receive the device address.
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Product Preview
WM8593
When the WM8593 has acknowledged a correct address, the controller sends the first byte of control data (A6 to A0, i.e. the WM8593 initial register address). The WM8593 then acknowledges the first control data byte by pulling SDIN low for one SCLK pulse. The controller then sends a byte of register data. The WM8593 acknowledges the first byte of register data, auto-increments the register address to be written to, and waits for the next byte of register data. Subsequent bytes of register data can be written to consecutive registers of the WM8593 without setting up the device and register address. The transfer of data is complete when there is a low to high transition on SDIN while SCLK is high.
Figure 7 2-Wire Auto-Increment Register Write
REGISTER READBACK
The WM8593 allows readback of all registers with data output on the bidirectional SDIN pin. The protocol is similar to that used to write to the device. The controller will issue the device address followed by a write bit, and the register index will then be passed to the WM8593. At this point the controller will issue a repeated start condition and resend the device address along with a read bit. The WM8593 will acknowledge this and the WM8593 will become a slave transmitter. The WM8593 will place the data from the indexed register onto SDIN MSB first. When the controller receives the first byte of data, it acknowledges it. When the controller receives the second and final byte of data it will not acknowledge receipt of the data indicating that it will resume master transmitter control of SDIN. The controller will then issue a stop command completing the read cycle.
Figure 8 2-wire Read Protocol
AUTO-INCREMENT REGISTER READBACK
It is possible to read from multiple consecutive registers in continuous readback mode. Continuous readback mode is selected by setting AUTO_INC. In continuous readback mode, the WM8593 will return the indexed register first, followed by consecutive registers in increasing index order until the controller issues a stop sequence.
Figure 9 2-Wire Auto-Increment Register Readback
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WM8593
3-WIRE (SPI COMPATIBLE) SERIAL CONTROL INTERFACE MODE
REGISTER WRITE
Product Preview
SDIN is used for the program data, SCLK is used to clock in the program data and /CS is use to latch in the program data. SDIN is sampled on the rising edge of SCLK. The 3-wire interface write protocol is shown in Figure 10.
Figure 10 3-Wire Serial Interface Write Protocol * * * * W indicates write operation. A[6:0] is the register index. B[15:0] is the data to be written to the register indexed. /CS is edge sensitive - the data is latched on the rising edge of /CS.
REGISTER READ-BACK
The read-only status registers can be read back via the SDOUT pin. Read Back is enabled when the R/W bit is high. The data can then be read by writing to the appropriate register address, to which the device will respond with data.
Figure 11 3-Wire Serial Interface Readback Protocol
REGISTER RESET
Any write to register R0 (00h) will reset the WM8593. All register bits are reset to their default values.
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Product Preview
WM8593
DEVICE ID AND REVISION
Reading from register R0 returns the device ID. Reading from register R1 returns the device revision number. REGISTER ADDRESS R0 DEVICE_ID 00h R1 REVISION 01h BIT 15:0 LABEL DEVICE_ID [15:0] REVNUM [7:0] DEFAULT 10000101 10010011 N/A DESCRIPTION Device ID A read of this register will return the device ID, 0x8593. Device Revision A read of this register will return the device revision number. This number is sequentially incremented if the device design is updated.
7:0
Table 9 Device ID and Revision Number
GLOBAL ENABLE CONTROL
The WM8593 includes a number of enable and disable mechanisms to allow the device to be powered on and off in a pop-free manner. A global enable control bit enables the ADC, DAC and analogue paths. REGISTER ADDRESS R12 ENABLE 0Ch BIT 0 LABEL GLOBAL_ EN DEFAULT 0 DESCRIPTION Device Global Enable 0 = ADC, DAC and PGA ramp control circuitry disabled 1 = ADC, DAC and PGA ramp control circuitry enabled
Table 10 Global Enable Control
DIGITAL AUDIO INTERFACE
Digital audio data is transferred to and from the WM8593 via the digital audio interface. The DACs have independent data inputs and master clocks, bit clocks and left/right frame clocks, and operate in both master or slave mode The ADC has independent master clock, bit clock and left/right frame clock in addition to its data output, and can operate in both master and slave modes.
MASTER MODE
The ADC audio interface requires both a left/right frame clock (ADCLRCLK) and a bit clock (ADCBCLK). These can be supplied externally (slave mode) or they can be generated internally (master mode). Selection of master and slave mode is achieved by setting ADC_MSTR in ADC Control Register 3. The frequency of ADCLRCLK in master mode is dependent upon the ADC master clock frequency and the ADC_SR[2:0] bits. The frequency of ADCBCLK in master mode can be selected by ADC_BCLKDIV[1:0]. The DAC audio interfaces require both left/right frame clocks (DACLRCLK1, DACLRCLK2) and bit clocks (DACBCLK1, DACBCLK2). These can be supplied externally (slave mode) or they can be generated internally (master mode). Selection of master and slave mode is achieved by setting DAC1_MSTR in DAC1 Control Register 3 and DAC2_MSTR in DAC2 Control Register 3. The frequency of DACLRCLK1 in master mode is dependent upon the DAC1 master clock frequency and the DAC1_SR[2:0] bits. Similarly the frequency of DACLRCLK2 in master mode is dependent upon the DAC2 master clock frequency and the DAC2_SR[2:0] bits. The frequency of DACBCLK1 and DACBCLK2 in master mode can be selected by DAC1_BCLKDIV[1:0] and DAC2_BCLKDIV[1:0].
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WM8593
REGISTER ADDRESS R3 DAC1_CTRL2 03h BIT 2:0 LABEL DAC1_ SR[2:0] DEFAULT 000
Product Preview DESCRIPTION DAC MCLK:LRCLK Ratio 000 = Auto detect 001 = 128fs 010 = 192fs 011 = 256fs 100 = 384fs 101 = 512fs 110 = 768fs 111 = 1152fs DAC1 BCLK Rate 000 = MCLK / 4 001 = MCLK / 8 010 = 32fs 011 = 64fs 100 = 128fs All other values of DAC1_BCLKDIV[2:0] are reserved DAC1 Master Mode Select 0 = Slave mode, DACBCLK1 and DACLRCLK1 are inputs to WM8593 1 = Master mode, DACBCLK1 and DACLRCLK1 are outputs from WM8593 DAC MCLK:LRCLK Ratio 000 = Auto detect 001 = 128fs 010 = 192fs 011 = 256fs 100 = 384fs 101 = 512fs 110 = 768fs 111 = 1152fs DAC2 BCLK Rate 000 = MCLK / 4 001 = MCLK / 8 010 = 32fs 011 = 64fs 100 = 128fs All other values of DAC2_BCLKDIV[2:0] are reserved DAC2 Master Mode Select 0 = Slave mode, DACBCLK2 and DACLRCLK2 are inputs to WM8593 1 = Master mode, DACBCLK2 and DACLRCLK2 are outputs from WM8593 ADC MCLK:LRCLK Ratio 000 = Auto detect 001 = 128fs 010 = 192fs 011 = 256fs 100 = 384fs 101 = 512fs 110 = 768fs 111 = Reserved ADC BCLK Rate PP Rev 1.0 January 2007 22
5:3
DAC1_ BCLKDIV [2:0]
000
R4 DAC1_CTRL3 04h
0
DAC1_ MSTR
0
R8 DAC1_CTRL2 08h
2:0
DAC2_ SR[2:0]
000
5:3
DAC2_ BCLKDIV [2:0]
000
R9 DAC2_CTRL3 09h
0
DAC2_ MSTR
0
R14 ADC_CTRL2 0Eh
2:0
ADC_ SR[2:0]
000
5:3
ADC_BCLK
000
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Product Preview
WM8593
REGISTER ADDRESS BIT LABEL DIV[2:0] DEFAULT DESCRIPTION 000 = MCLK / 4 001 = MCLK / 8 010 = 32fs 011 = 64fs 100 = 128fs All other values of ADC_BCLKDIV[2:0] are reserved 0 ADC Master Mode Select 0 = Slave mode, ADCBCLK and ADCLRCLK are inputs to WM8593 1 = Master mode, ADCBCLK and ADCLRCLK are outputs from WM8593
R15 ADC_CTRL3 0Fh
0
ADC_ MSTR
Table 11 ADC Master Mode Control
SLAVE MODE
In slave mode, the master clock to left/right clock ratio can be auto-detected or set manually by register write. REGISTER ADDRESS R3 DAC1_CTRL2 03h R8 DAC2_CTRL2 08h BIT 2:0 LABEL DAC1_ SR[2:0] DAC2_ SR[2:0] DEFAULT 000 DESCRIPTION DAC MCLK:LRCLK Ratio 000 = Auto detect 001 = 128fs 010 = 192fs 011 = 256fs 100 = 384fs 101 = 512fs 110 = 768fs 111 = 1152fs ADC MCLK:LRCLK Ratio 000 = Auto detect 001 = reserved 010 = reserved 011 = 256fs 100 = 384fs 101 = 512fs 110 = 768fs 111 = Reserved
2:0
000
R14 ADC_CTRL2 0Eh
2:0
ADC_ SR[2:0]
000
Table 12 Slave Mode MCLK to LRCLK Ratio Control
DIGITAL AUDIO DATA SAMPLING RATES
In a typical digital audio system there is one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system's master clock. The WM8593 uses independent master clocks for ADC and DACs. The external master clocks can be applied directly to the ADCMCLK, DACMCLK1 and DACMCLK2 input pins. In a system where there are a number of possible sources for the reference clock, it is recommended that the clock source with the lowest jitter be used for the master clock to optimise the performance of the WM8593.
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WM8593
Product Preview In slave clocking mode the WM8593 has a master detection circuit that automatically determines the relationship between the master clock frequency (ADCMCLK, DACMCLK1, DACMCLK2) and the sampling rate (ADCLRCLK, DACLRCLK1, DACLRCLK2), to within +/- 32 system clock periods. The master clocks must be synchronised with the left/right clocks, although the device is tolerant of phase variations or jitter on the master clocks. The ADC supports master clock to sampling clock ratios of 256fs to 768fs and sampling rates of 32kHz to 96kHz, provided the internal signal processing of the ADC is programmed to operate at the correct rate. The DACs support master clock to sampling clock ratios of 128fs to 1152fs and sampling rates of 32kHz to 192kHz, provided the internal signal processing of the DACs is programmed to operate at the correct rate. Table 13 shows typical master clock frequencies and sampling rates supported by the WM8593 ADC. Table 14 shows typical master clock frequencies and sampling rates supported by the WM8593 DACs. MASTER CLOCK FREQUENCY (MHZ)
Sampling Rate (ADCLRCLK) 32kHz 44.1kHz 48kHz 88.2kHz 96kHz
256fs 8.192 11.2896 12.288 22.5792 24.576
384fs 12.288 16.9344 18.432 33.8688 Unavailable
512fs 16.384 22.5792 24.576 Unavailable Unavailable
768fs 24.576 33.8688 36.864 Unavailable Unavailable
Table 13 ADC Master Clock Frequency Versus Sampling Rate Sampling Rate (DACLRCLK1 DACLRCLK2) 32kHz 44.1kHz 48kHz 88.2kHz 96kHz 176.4kHz 192kHz 128fs Unavailable Unavailable Unavailable 11.2896 12.288 22.5792 24.576 192fs Unavailable 8.4672 9.216 16.9344 18.432 33.8688 36.864 MASTER CLOCK FREQUENCY (MHZ) 256fs 8.192 11.2896 12.288 22.5792 24.576 Unavailable Unavailable 384fs 12.288 16.9344 18.432 33.8688 36.864 Unavailable Unavailable 512fs 16.384 22.5792 24.576 Unavailable Unavailable Unavailable Unavailable 768fs 24.576 33.8688 36.864 Unavailable Unavailable Unavailable Unavailable 1152fs 36.864 Unavailable Unavailable Unavailable Unavailable Unavailable Unavailable
Table 14 DAC Master Clock Frequency Versus Sampling Rate
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WM8593
DIGITAL AUDIO DATA FORMATS
The WM8593 supports a range of common audio interface formats: * * * * * I2S Left Justified (LJ) Right Justified (RJ) DSP Mode A DSP Mode B
All formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the exception of 32 bit RJ mode, which is not supported. Audio data for each stereo channel is time multiplexed with the interface's left/right clock indicating whether the left or right channel is present. The left/right clock is also used as a timing reference to indicate the beginning or end of the data words. In LJ, RJ and I2S modes, the minimum number of bit clock periods per left/right clock period is two times the selected word length. The left/right clock must be high for a minimum of bit clock periods equivalent to the word length, and low for the same period. For example, for a word length of 24 bits, the left/right clock must be high for a minimum of 24 bit clock periods and low for a minimum of 24 bit clock periods. Any mark to space ratio is acceptable for the left/right clock provided these requirements are met. In DSP modes A and B, left and right channels must be time multiplexed and input on DIN1. LRCLK is used as a frame synchronisation signal to identify the MSB of the first input word. The minimum number of bit clock periods per left/right clock period is two times the selected word length. Any mark to space ratio is acceptable for the left/right clock provided the rising edge is correctly positioned.
I2S MODE
In I2S mode, the MSB of input data is sampled on the second rising edge of bit clock following a left/right clock transition. The MSB of output data changes on the first falling edge of bit clock following a left/right clock transition, and may be sampled on the next rising edge of bit clock. Left/right clocks are low during the left channel audio data samples and high during the right channel audio data samples.
Figure 12 I2S Mode Timing
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LEFT JUSTIFIED (LJ) MODE
Product Preview
In LJ mode, the MSB of the input data is sampled by the WM8593 on the first rising edge of bit clock following a left/right clock transition. The MSB of output data changes on the same falling edge of bit clock as left/right clock and may be sampled on the next rising edge of bit clock. Left/right clock is high during the left channel audio data samples and low during the right channel audio data samples.
Figure 13 LJ Mode Timing
RIGHT JUSTIFIED (RJ) MODE
In RJ mode the LSB of input data is sampled on the rising edge of bit clock preceding a left/right clock transition. The LSB of output data changes on the falling edge of bit clock preceding a left/right clock transition, and may be sampled on the next rising edge of bit clock. Left/right clock is high during the left channel audio data samples and low during the right channel audio data samples.
Figure 14 RJ Mode Timing
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WM8593
DSP MODE A
In DSP Mode A, the MSB of channel 1 left data input is sampled on the second rising edge of bit clock following a left/right clock rising edge. Channel 1 right data then follows. The MSB of output data changes on the first falling edge of bit clock following a left/right clock transition and may be sampled on the rising edge of bit clock. The right channel data is contiguous with the left channel data.
Figure 15 DSP Mode A Timing
DSP MODE B
In DSP Mode B, the MSB of channel 1 left data input is sampled on the first bit clock rising edge following a left/right clock rising edge. Channel 1 right data then follows. The MSB of output data changes on the same falling edge of BCLK as the low to high left/right clock transition and may be sampled on the rising edge of bit clock. The right channel data is contiguous with the left channel data.
Figure 16 DSP Mode B Timing
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DIGITAL AUDIO INTERFACE CONTROL
Product Preview
The control of the audio interface formats is achieved by register write. Dynamically changing the audio data format may cause erroneous operation and is not recommended. Interface timing is such that the input data and left/right clock are sampled on the rising edge of the interface bit clock. Output data changes on the falling edge of the interface bit clock. By setting the appropriate bit clock and left/right clock polarity bits, the WM8593 ADC and DACs can sample data on the opposite clock edges. The control of audio interface formats and clock polarities is summarised in Table 15. REGISTER ADDRESS R2 DAC1_CTRL1 02h BIT 1:0 LABEL DAC1_ FMT[1:0] DEFAULT 10 DESCRIPTION DAC1 Audio Interface Format 00 = Right Justified 01 = Left Justified 10 = I2S 11 = DSP DAC1 Audio Interface Word Length 00 = 16-bit 01 = 20-bit 10 = 24-bit 11 = 32-bit (not available in Right Justified mode) DAC1 BCLK Polarity 0 = DACBCLK not inverted - data latched on rising edge of BCLK 1 = DACBCLK inverted - data latched on falling edge of BCLK DAC1 LRCLK Polarity 0 = DACLRCLK not inverted 1 = DACLRCLK inverted DAC2 Audio Interface Format 00 = Right Justified 01 = Left Justified 10 = I2S 11 = DSP DAC2 Audio Interface Word Length 00 = 16-bit 01 = 20-bit 10 = 24-bit 11 = 32-bit (not available in Right Justified mode) DAC2 BCLK Polarity 0 = DACBCLK not inverted - data latched on rising edge of BCLK 1 = DACBCLK inverted - data latched on falling edge of BCLK DAC2 LRCLK Polarity 0 = DACLRCLK not inverted 1 = DACLRCLK inverted ADC Audio Interface Format 00 = Right Justified 01 = Left Justified 10 = I2S 11 = DSP
3:2
DAC1_ WL[1:0]
10
4
DAC1_BCP
0
5
DAC1_LRP
0
R7 DAC2_CTRL1 07h
1:0
DAC2_ FMT[1:0]
10
3:2
DAC2_ WL[1:0]
10
4
DAC2_BCP
0
5
DAC2_LRP
0
R13 ADC_CTRL1 0Dh
1:0
ADC_ FMT[1:0]
10
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WM8593
REGISTER ADDRESS BIT 3:2 LABEL ADC_ WL[1:0] DEFAULT 10 DESCRIPTION ADC Audio Interface Word Length 00 = 16-bit 01 = 20-bit 10 = 24-bit 11 = 32-bit (not available in Right Justified mode) ADC BCLK Polarity 0 = ADCBCLK not inverted - data latched on rising edge of BCLK 1 = ADCBCLK inverted - data latched on falling edge of BCLK ADC LRCLK Polarity 0 = ADCLRCLK not inverted 1 = ADCLRCLK inverted
4
ADC_BCP
0
5
ADC_LRP
0
Table 15 Audio Interface Control
DAC FEATURES
The WM8593 includes two 24-bit DACs with independent clocks and independent data inputs. The DACs include digital volume control with zero cross and soft mute, de-emphasis support, and the capability to select the output channels to be stereo or a range of mono options. The DACs are enabled by writing to DAC1_EN and DAC2_EN. REGISTER ADDRESS R2 DAC1_CTRL1 02h R7 DAC2_CTRL1 07h BIT 8 LABEL DAC1_EN DEFAULT 0 DESCRIPTION DAC1 Enable 0 = DAC disabled 1 = DAC enabled DAC2 Enable 0 = DAC2 disabled 1 = DAC2 enabled
8
DAC2_EN
0
Table 16 DAC Enable Control
DIGITAL VOLUME CONTROL
The WM8593 DACs include independent digital volume control, allowing the digital gain to be adjusted between -100dB and +12dB in 0.5dB steps. All four DAC channels can be controlled independently. Alternatively, global update bits allow the user to write all volume changes before the volume is updated. Volume control includes optional zero cross functionality. When zero cross is enabled, volume changes are not applied until the output level crosses VMID. Zero cross helps to prevent pop and click noise when changing volume settings. REGISTER ADDRESS R5 DAC1L_VOL 05h R6 DAC1R_VOL 06h R10 DAC2L_VOL 0Ah BIT 7:0 LABEL DAC1L _VOL[7:0] DAC1R _VOL[7:0] DAC2L _VOL[7:0] DEFAULT 11001000 DESCRIPTION DAC Digital Volume 0000 0000 = -100dB 0000 0001 = -99.5dB 0000 0010 = -99dB ...0.5dB steps 1100 1000 = 0dB ...0.5dB steps 1101 1111 = +11.5dB 111X XXXX = +12dB
7:0
7:0
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REGISTER ADDRESS R11 DAC2R_VOL 0Bh R5 DAC1L_VOL 05h R6 DAC1R_VOL 06h R10 DAC2L_VOL 0Ah R11 DAC2R_VOL 0Bh R2 DAC1_CTRL1 02h R7 DAC2_CTRL1 07h BIT 7:0 LABEL DAC2R _VOL[7:0] DAC1L_VU 0 DEFAULT
Product Preview DESCRIPTION
8
8
DAC1R_VU
DAC Digital Volume Update 0 = Latch DAC volume setting into Register Map but do not update volume 1 = Latch DAC volume setting into Register Map and update left and right channels simultaneously
8
DAC2L_VU
8
DAC2R_VU
7
DAC1 _ZCEN DAC2 _ZCEN
1
7
DAC Digital Volume Control Zero Cross Enable 0 = Do not use zero cross 1 = Use zero cross
Table 17 DAC Digital Volume Control
SOFTMUTE
A soft mute can be applied to DAC1 and DAC2 independently. REGISTER ADDRESS R2 DAC1_CTRL1 02h R7 DAC2_CTRL1 07h BIT 9 LABEL DAC1_ MUTE DAC2_ MUTE DEFAULT 0 DESCRIPTION DAC Softmute 0 = Normal operation 1 = Softmute applied
9
0
Table 18 DAC Softmute Control
DIGITAL MONOMIX CONTROL
Each DAC can be independently set to output a range of mono and stereo options. Each DAC output channel can output left channel data, right channel data or a mix of left and right channel data. REGISTER ADDRESS R2 DAC1_CTRL1 02h BIT 11:10 LABEL DAC1_OP _MUX[1:0] DEFAULT 00 DESCRIPTION DAC1 Digital Monomix 00 = Stereo (Normal Operation) 01 = Mono (Left data to DAC1R) 10 = Mono (Right data to DAC1L) 11 = Digital Monomix, (L+R)/2 DAC2 Digital Monomix 00 = Stereo (Normal Operation) 01 = Mono (Left data to DAC2R) 10 = Mono (Right data to DAC2L) 11 = Digital Monomix, (L+R)/2
R7 DAC2_CTRL1 07h
11:10
DAC2_OP _MUX[1:0]
00
Table 19 Digital Monomix Control
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WM8593
DE-EMPHASIS
A digital de-emphasis filter may be applied to the DAC outputs when the sampling frequency is 44.1kHz. The de-emphasis filter for each DAC can be applied independently. The deemphasis filter responses and error can be seen in Figure 67 and Figure 68. REGISTER ADDRESS R2 DAC1_CTRL1 02h R7 DAC2_CTRL1 07h BIT 6 LABEL DAC1 _DEEMPH DAC2 _DEEMPH DEFAULT 0 DESCRIPTION DAC1 De-emphasis 0 = No de-emphasis 1 = Apply 44.1kHz de-emphasis DAC2 De-emphasis 0 = No de-emphasis 1 = Apply 44.1kHz de-emphasis
6
0
Table 20 De-emphasis Control
ADC FEATURES
The WM8593 features a stereo 24-bit sigma-delta ADC, digital volume control with zero cross, a selectable high pass filter to remove DC offsets, and support for both master and slave clocking modes. REGISTER ADDRESS R13 ADC_CTRL1 0Dh BIT 6 LABEL ADC_EN DEFAULT 0 DESCRIPTION ADC Enable 0 = ADC disabled 1 = ADC enabled
Table 21 ADC Enable Control
DIGITAL VOLUME CONTROL
The ADC digital volume can be adjusted between +30dB and -97dB in 0.5dB steps. Left and right channels can be controlled independently. Volume changes can be applied immediately to each channel, or volume changes can be written to both channels before writing to an update bit in order to change the volume in both channels simultaneously. Volume control includes optional zero cross functionality. When zero cross is enabled, volume changes are not applied until the output level crosses the DC level of the ADC output. Zero cross helps to prevent pop and click noise when changing volume settings. REGISTER ADDRESS R16 ADCL_VOL 10h R17 ADCR_VOL 11h BIT 7:0 LABEL ADCL _VOL[7:0] ADCR _VOL[7:0] DEFAULT 11000011 DESCRIPTION ADC Digital Volume 0000 0000 = Digital mute 0000 0001 = -97dB 0000 0010 = -96.5dB ...0.5dB steps 1100 0011 = 0dB ...0.5dB steps 1111 1110 = +29.5dB 1111 1111 = +30dB ADC Digital Volume Update 0 = Latch ADC volume setting into Register Map but do not update volume 1 = Latch ADC volume setting into Register Map and update left and right channels simultaneously
7:0
11000011
R16 ADCL_VOL 10h R17 ADCR_VOL 11h
8
ADCL_VU
0
8
ADCR_VU
0
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REGISTER ADDRESS R13 ADC_CTRL1 0Dh BIT 13 LABEL ADC_ZC_ EN DEFAULT 1
Product Preview DESCRIPTION ADC Digital Volume Control Zero Cross Enable 0 = Do not use zero cross, change volume instantly 1 = Use zero cross, change volume when data crosses zero
Table 22 ADC Digital Volume Control
CHANNEL SWAP AND INVERSION
The WM8593 ADC input channels can be inverted and swapped in a number of ways to provide maximum flexibility of input path to the ADC. The default configuration provides stereo output data with the left and right channel data in the left and right channels. It is possible to swap the left and right channels, invert them independently, or select the same data from both channels. REGISTER ADDRESS R13 ADC_CTRL1 0Dh BIT 7 LABEL ADC_ LRSWAP DEFAULT 0 DESCRIPTION ADC Left/Right Swap 0 = Normal 1 = Swap left channel data into right channel and vice-versa ADCL and ADCR Output Signal Inversion 0 = Output not inverted 1 = Output inverted ADC Data Output Select 00 = left data from ADCL, right data from ADCR 01 = left data from ADCL, right data from ADCL 10 = left data from ADCR, right data from ADCR 11 = left data from ADCR, right data from ADCL
8 9 11:10
ADCR_ INV ADCL_ INV ADC_ DATA_ SEL[1:0]
0 0 00
Table 23 ADC Channel Swap Control
HIGH PASS FILTER
The WM8593 includes a high pass filter to remove DC offsets. The high pass filter response is shown on page 93. It is possible to disable the high pass filter by writing to ADC_HPD. REGISTER ADDRESS R13 ADC_CTRL1 0Dh BIT 12 LABEL ADC_HPD DEFAULT 0 DESCRIPTION ADC High Pass Filter Disable 0 = High pass filter enabled 1 = High pass filter disabled
Table 24 High Pass Filter Disable Control
ANALOGUE ROUTING CONTROL
The WM8593 has a number of analogue paths, allowing flexible routing of a number of analogue input signals and DAC output signals at levels up to 2Vrms. The analogue paths include volume control with zero cross, optional soft ramp and soft mute, and flexible routing of analogue inputs and DAC outputs to analogue outputs. There are a total of 16 (eight stereo) analogue input channels and four (two stereo) DAC output channels. Any two of the sixteen input channels can be routed to the ADC. Any six of the 20 total channels can be routed to the analogue outputs.
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WM8593
Figure 17 illustrates the various blocks of the analogue routing paths within the WM8593. The following sections describe the control bits associated with the WM8593 analogue paths. Figure 17 also shows where these control bits take affect on the WM8593.
Figure 17 Analogue Routing Paths and Control
ANALOGUE VOLUME CONTROL
Each analogue bypass channel includes analogue volume control. Volume changes can be applied to each channel immediately as they are written. Alternatively, all volume changes can be written, and then all volume changes can be applied simultaneously using the volume update feature. Volume control includes optional zero cross functionality. When zero cross is enabled, volume changes are not applied until the output level crosses the DC level of the analogue channel (VMID). Zero cross helps to prevent pop and click noise when changing volume settings. The zero cross function includes a timeout which forces volume changes if a zero cross event does not occur. The timeout period is a maximum of 278ms. REGISTER ADDRESS R19 PGA1L_VOL 13h R20 PGA1R_VOL 14h R21 PGA2L_VOL 15h R22 PGA2R_VOL 16h BIT 7:0 LABEL PGA1L_ VOL[7:0] PGA1R_ VOL[7:0] PGA2L_ VOL[7:0] PGA2R_ VOL[7:0] DEFAULT 00001100 DESCRIPTION Input PGA Volume 0000 0000 = +6dB 0000 0001 = +5.5dB ...0.5dB steps 00001100 = 0dB ... 1001 1110 = -73.5dB 1001 1111 = PGA Mute
7:0
7:0
7:0
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WM8593
REGISTER ADDRESS R23 PGA3L_VOL 17h R24 PGA3R_VOL 18h R19 PGA1L_VOL 13h R20 PGA1R_VOL 14h R21 PGA2L_VOL 15h R22 PGA2R_VOL 16h R23 PGA3L_VOL 17h R24 PGA3R_VOL 18h R25 PGA_CTRL1 19h BIT 7:0 LABEL PGA3L_ VOL[7:0] PGA3R_ VOL[7:0] PGA1L_ VU PGA1R_ VU PGA2L_ VU PGA2R_ VU PGA3L_ VU PGA3R_ VU PGA1L_ ZC PGA1R_ ZC PGA1L_ ZC PGA1R_ ZC PGA1L_ ZC PGA1R_ ZC 1 0 DEFAULT
Product Preview DESCRIPTION
7:0
8
8
Input PGA Volume Update 0 = Latch corresponding volume setting into Register Map but do not update volume 1 = Latch corresponding volume setting into Register Map and update all channels simultaneously
8
8
8
8
2 3 4 5 6 7
PGA Gain Zero Cross Enable 0 = PGA gain updates occur immediately 1 = PGA gain updates occur on zero cross
Table 25 Analogue Volume Control
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WM8593
VOLUME RAMP
Analogue volume can be adjusted by step change or by soft ramp. The ramp rate is dependent upon the sampling rate. The sampling rate upon which the volume ramp rate is based can be selected between the DAC sampling rate or the ADC sampling rate in either slave mode or master mode. The ramp rates for common audio sample rates are shown in Table 26: SAMPLE RATE FOR PGA (kHz) 32 44.1 48 88.2 96 176.4 192 Table 26 Analogue Volume Ramp Rate For example, when using a sample rate of 48kHz, the time taken for a volume change from and initial setting of 0dB to -20dB is calculated as follows: Volume Change (dB) x PGA Ramp Rate (ms/dB) = 20 x 0.33 = 6.6ms When changing from one PGA ramp clock source to another, it is recommended that PGA_SAFE_SW is set to 0. This forces the clock switch over to occur at a point where all relevant clock signals are zero, ensuring glitch-free operation. This process can take up to 32 left/right clock cycles. If a faster change in PGA ramp rate clock source is required, PGA_FORCE can be set to 1. This forces the change in clock source to occur immediately regardless of the state of the relevant clock signals internally. Glitch-free operation is not guaranteed under these conditions. PGA_FORCE must be set back to 0 to initialise the timing circuits with the new clock. If the volume ramp function is not required when increasing or decreasing volume, this block can be bypassed by setting ATTACK_BYPASS or DECAY_BYPASS to 1. Figure 18 shows the effect of these register settings: DIVIDE BY 8 8 8 16 16 32 32 PGA RAMP RATE (ms/dB) 0.50 0.36 0.33 0.36 0.33 0.36 0.33
Figure 18 ATTACK_BYPASS and DECAY_BYPASS Functionality
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WM8593
Product Preview Note: When ATTACK_BYPASS=1 or DECAY_BYPASS=1, it is recommended that the zero cross function for the PGA is used to eliminate click noise when changing volume settings. REGISTER ADDRESS R25 PGA_CTRL1 19h BIT 0 LABEL DECAY_ BYPASS ATTACK_ BYPASS PGA_ SR[2:0] DEFAULT 0 DESCRIPTION PGA Gain Decay Mode 0 = PGA gain will ramp down 1 = PGA gain will step down PGA Gain Attack Mode 0 = PGA gain will ramp up 1 = PGA gain will step up Sample Rate for PGA 000 = 32kHz 001 = 44.1kHz 010 = 48kHz 011 = 88.2kHz 100 = 96kHz 101 = 176.4kHz 11X = 192kHz See Table 26 for further information on PGA sample rate versus volume ramp rate. PGA Ramp Control Clock Source Mux Force Update 0 = Wait until clocks are safe before switching PGA clock source 1 = Force PGA clock source to change immediately PGA Ramp Control Clock Source 000 = LRCLK1 001 = LRCLK2 010 = LRCLK3 011 = LRCLK4 100 = LRCLK5 101 = DACLRCLK1 (when DAC1 is being used in master mode) 110 = DACLRCLK2 (when DAC2 is being used in master mode) 111 = ADCLRCLK (when ADC is being used in master mode) PGA Ramp Control Clock Source Mux Update 0 = Do not update PGA clock source 1 = Update clock source
1
0
R27 ADD_CTRL1 1Bh
6:4
001
R36 PGA_CTRL3 24h
0
PGA_ FORCE
0
3:1
PGA_ SEL[2:0]
000
10
PGA_UPD
0
Table 27 Analogue Volume Ramp Control
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WM8593
ANALOGUE MUTE CONTROL
The analogue channel output drivers can be muted independently and are muted by default. Alternatively, all mute bits can be set using a master mute bit, MUTE_ALL.
REGISTER ADDRESS R26 PGA_CTRL2 1Ah
BIT 0
LABEL MUTE_ ALL VOUT1L_ MUTE VOUT1R_ MUTE VOUT2L_ MUTE VOUT2R_ MUTE VOUT3L_ MUTE VOUT3R_ MUTE
DEFAULT 0
DESCRIPTION Master Output Driver Mute Control 0 = Unmute all Output Drivers 1 = Mute all Output Drivers Individual Output Driver Mute Control 0 = Unmute Output Driver 1 = Mute Output Driver
1 2 3 4 5 6
1 1 1 1 1 1
Table 28 Analogue Mute Control
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INPUT SELECTOR CONTROL
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Each left channel input PGA can select between all left channel analogue inputs, and both left and right DAC inputs. Each right channel input PGA can select between all right channel analogue inputs, and both left and right DAC inputs. All PGAs can be enabled and disabled independently. Note: It is recommended to mute the PGA before changing the input to the PGA to avoid pop/click noises when selecting a different input source.
Figure 19 Input Selector Control
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WM8593
REGISTER ADDRESS R28 INPUT_CTRL1 1Ch
BIT 3:0
LABEL PGA1L_ IN_ SEL[3:0] PGA2L_ IN_ SEL[3:0] PGA3L_ IN_ SEL[3:0]
DEFAULT 0000
DESCRIPTION Left Input PGA Source Selection 0000 = No input selected 0001 = VIN1L selected 0010 = VIN2L selected 0011 = VIN3L selected 0100 = VIN4L selected 0101 = VIN5L selected 0110 = VIN6L selected 0111 = VIN7L selected 1000 = VIN8L selected 1001 = DAC1L output selected 1010 = DAC1R output selected 1011 = DAC2L output selected 1100 = DAC2R output selected 1101 to 1111 = reserved Right Input PGA Source Selection 0000 = No input selected 0001 = VIN1R selected 0010 = VIN2R selected 0011 = VIN3R selected 0100 = VIN4R selected 0101 = VIN5R selected 0110 = VIN6R selected 0111 = VIN7R selected 1000 = VIN8R selected 1001 = DAC1L output selected 1010 = DAC1R output selected 1011 = DAC2L output selected 1100 = DAC2R output selected 1101 to 1111 = reserved Input PGA Enable Controls 0 = PGA disabled 1 = PGA enabled
11:8
0000
R29 INPUT_CTRL2 1Dh
7:4
0000
R28 INPUT_CTRL1 1Ch R29 INPUT_CTRL2 1Dh
7:4
PGA1R_ IN_ SEL[3:0] PGA2R_ IN_ SEL[3:0] PGA3R_ IN_ SEL[3:0]
0000
3:0
0000
11:8
0000
R31 INPUT_CTRL4 1Fh
0 1 2 3 4 5
PGA1L_ EN PGA1R_ EN PGA2L_ EN PGA2R_ EN PGA3L_ EN PGA3R_ EN
0
Table 29 PGA Input Select Control
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ADC INPUT SELECTOR CONTROL
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The ADC input switch can be configured to allow any combination of two inputs to be input to the ADC. Each input switch channel can be controlled independently. The input switch also includes PGAs to provide a range of analogue gain settings between 0dB and +12dB prior to the ADC. These PGAs can be enabled and disabled independently.
Figure 20 ADC Input Selector Control
REGISTER ADDRESS R30 INPUT_CTRL3 1Eh
BIT 3:0 7:4
LABEL ADCL_ SEL[3:0] ADCR_ SEL[4:0]
DEFAULT 0000 0000
DESCRIPTION ADC Input Select 0000 = VIN1L 0001 = VIN2L 0010 = VIN3L 0011 = VIN4L 0100 = VIN5L 0101 = VIN6L 0110 = VIN7L 0111 = VIN8L 1000 = VIN1R 1001 = VIN2R 1010 = VIN3R 1011 = VIN4R 1100 = VIN5R 1101 = VIN6R 1110 = VIN7R 1111 = VIN8R ADC Amplifier Gain Control 00 = 0dB 01 = +3dB 10 = +6dB 11 = +12dB ADC Input Switch Control 0 = ADC input switches open 1 = ADC input switches closed
9:8
ADC_AMP _VOL[1:0]
10
10
ADC_ SWITCH_ EN
0
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WM8593
REGISTER ADDRESS R31 INPUT_CTRL4 1Fh BIT 6 7 LABEL ADCL_ AMP_EN ADCR_ AMP_EN DEFAULT 0 0 DESCRIPTION ADC Input Amplifier Enable Controls 0 = Amplifier disabled 1 = Amplifier enabled
Table 30 ADC Input Switch Control
OUTPUT SELECTOR CONTROL
Any analogue PGA channel can be routed to any analogue output. All analogue outputs can be independently enabled and disabled. Additionally, all outputs can be tri-stated to allow the output to be connected to applications where ports can either be inputs or outputs. Note: It is recommended to mute all the outputs before changing the output selector to avoid pop/click noises when selecting a different output source.
Figure 21 Output Selector Control
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WM8593
REGISTER ADDRESS R32 OUTPUT_ CTRL1 20h BIT 2:0 5:3 8:6 R33 OUTPUT_ CTRL2 21h 2:0 5:3 8:6 R34 OUTPUT_ CTRL3 22h 0 1 2 3 4 5 7 8 9 10 11 12 LABEL VOUT1L_ SEL[2:0] VOUT1R_ SEL[2:0] VOUT2L_ SEL[2:0] VOUT2R_ SEL[2:0] VOUT3L_ SEL[2:0] VOUT3R_ SEL[2:0] VOUT1L_ TRI VOUT1R_ TRI VOUT2L_ TRI VOUT1R_ TRI VOUT3L_ TRI VOUT3R_ TRI VOUT1L_ EN VOUT1R_ EN VOUT2L_ EN VOUT2R_ EN VOUT3L_ EN VOUT3R_ EN 0 Output Amplifier Enables 0 = Output amplifier disabled 1 = Output amplifier enabled DEFAULT 000 001 010 011 100 101 0
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DESCRIPTION Output Mux Selection 000 = PGA1L 001 = PGA1R 010 = PGA2L 011 = PGA2R 100 = PGA3L 101 = PGA3R 11X = Reserved
Output Amplifier Tristate Control 0 = Normal operation 1 = Output amplifier tristate enable (Hi-Z)
Table 31 Output Selection
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WM8593
DIGITAL ROUTING CONTROL
The WM8593 includes a highly flexible digital routing multiplexer, allowing several independent systems to be directly connected to the WM8593 without the need for glue logic. The WM8593 consists of five digital audio `ports', each with four pins, which can be configured to connect to any of the three internal WM8593 systems (ADC, DAC1 or DAC2) or to any other digital audio ports. Two GPIO pins are available as auxiliary bidirectional data pins when not used for jack detection. A simplified block diagram of the digital routing is shown in Figure 22:
Figure 22 Digital Routing Block Diagram
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DIGITAL AUDIO PORT PIN CONFIGURATION
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The MCLK1 and DIO1 pins are defined individually as an input or an output using MCLK1_SEL[2:0] and DIO1_SEL[2:0] respectively. The BCLK1 and LRCLK1 pins are always defined as inputs or outputs together using WORDCLK1_SEL[2:0].
REGISTER ADDRESS R37 AIF_MUX1 25h
BIT 3:1
LABEL MCLK1_ SEL[2:0]
DEFAULT 000
DESCRIPTION MCLK1 Pin Function Select 000 = Input to WM8593 001 = Output MCLK2 010 = Output MCLK3 011 = Output MCLK4 100 = Output MCLK5 101 to 111 = Reserved BCLK1 and LRCLK1 Pins Function Select 000 = Inputs to WM8593 001 = Output BCLK2 and LRCLK2 010 = Output BCLK3 and LRCLK3 011 = Output BCLK4 and LRCLK4 100 = Output BCLK5 and LRCLK5 101 = Output DAC1BCLK and DAC1LRCLK (when DAC1 is in master mode) 110 = Output DAC2BCLK and DAC2LRCLK (when DAC2 is in master mode) 111 = Output ADCBCLK and ADCBCLK (when ADC is master mode) DIO1 Pin Function Select 000 = Input to WM8593 001 = Source DIO2 010 = Source DIO3 011 = Source DIO4 100 = Source DIO5 101 = Source GPIO1 110 = Source GPIO2 111 = Source ADC Data Output
6:4
WORD CLK1_ SEL[2:0]
000
9:7
DIO1_ SEL[2:0]
000
Table 32 Digital Audio Port 1 Pin Configuration
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WM8593
The MCLK2 and DIO2 pins are defined individually as an input or an output using MCLK2_SEL[2:0] and DIO2_SEL[2:0] respectively. The BCLK2 and LRCLK2 pins are always defined as inputs or outputs together using WORDCLK2_SEL[2:0].
REGISTER ADDRESS R38 AIF_MUX2 26h
BIT 3:1
LABEL MCLK2_ SEL[2:0]
DEFAULT 001
DESCRIPTION MCLK2 Pin Function Select 000 = Output MCLK1 001 = Input to WM8593 010 = Output MCLK3 011 = Output MCLK4 100 = Output MCLK5 101 to 111 = Reserved BCLK2 and LRCLK2 Pins Function Select 000 = Output BCLK1 and LRCLK1 001 = Inputs to WM8593 010 = Output BCLK3 and LRCLK3 011 = Output BCLK4 and LRCLK4 100 = Output BCLK5 and LRCLK5 101 = Output DAC1BCLK and DAC1LRCLK (when DAC1 is in master mode) 110 = Output DAC2BCLK and DAC2LRCLK (when DAC2 is in master mode) 111 = Output ADCBCLK and ADCBCLK (when ADC is master mode) DIO2 Pin Function Select 000 = Output DIO1 001 = Input to WM8593 010 = Output DIO3 011 = Output DIO4 100 = Output DIO5 101 = Output GPIO1 110 = Output GPIO2 111 = Output ADC Data Output
6:4
WORD CLK2_ SEL[2:0]
001
9:7
DIO2_ SEL[2:0]
001
Table 33 Digital Audio Port 2 Pin Configuration
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Product Preview The MCLK3 and DIO3 pins are defined individually as an input or an output using MCLK3_SEL[2:0] and DIO3_SEL[2:0] respectively. The BCLK3 and LRCLK3 pins are always defined as inputs or outputs together using WORDCLK3_SEL[2:0].
REGISTER ADDRESS R39 AIF_MUX3 27h
BIT 3:1
LABEL MCLK3_ SEL[2:0]
DEFAULT 010
DESCRIPTION MCLK3 Pin Function Select 000 = Output MCLK1 001 = Output MCLK2 010 = Input to WM8593 011 = Output MCLK4 100 = Output MCLK5 101 to 111 = Reserved BCLK3 and LRCLK3 Pins Function Select 000 = Output BCLK1 and LRCLK1 001 = Output BCLK2 and LRCLK2 010 = Inputs to WM8593 011 = Output BCLK4 and LRCLK4 100 = Output BCLK5 and LRCLK5 101 = Output DAC1BCLK and DAC1LRCLK (when DAC1 is in master mode) 110 = Output DAC2BCLK and DAC2LRCLK (when DAC2 is in master mode) 111 = Output ADCBCLK and ADCBCLK (when ADC is master mode) DIO3 Pin Function Select 000 = Output DIO1 001 = Output DIO2 010 = Input to WM8593 011 = Output DIO4 100 = Output DIO5 101 = Output GPIO1 110 = Output GPIO2 111 = Output ADC Data Output
6:4
WORD CLK3_ SEL[2:0]
010
9:7
DIO3_ SEL[2:0]
010
Table 34 Digital Audio Port 3 Pin Configuration
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WM8593
The MCLK4 and DIO4 pins are defined individually as an input or an output using MCLK4_SEL[2:0] and DIO4_SEL[2:0] respectively. The BCLK4 and LRCLK4 pins are always defined as inputs or outputs together using WORDCLK4_SEL[2:0].
REGISTER ADDRESS R40 AIF_MUX4 28h
BIT 3:1
LABEL MCLK4_ SEL[2:0]
DEFAULT 011
DESCRIPTION MCLK4 Pin Function Select 000 = Output MCLK1 001 = Output MCLK2 010 = Output MCLK3 011 = Input to WM8593 100 = Output MCLK5 101 to 111 = Reserved BCLK4 and LRCLK4 Pins Function Select 000 = Output BCLK1 and LRCLK1 001 = Output BCLK2 and LRCLK2 010 = Output BCLK3 and LRCLK3 011 = Inputs to WM8593 100 = Output BCLK5 and LRCLK5 101 = Output DAC1BCLK and DAC1LRCLK (when DAC1 is in master mode) 110 = Output DAC2BCLK and DAC2LRCLK (when DAC2 is in master mode) 111 = Output ADCBCLK and ADCBCLK (when ADC is master mode) DIO4 Pin Function Select 000 = Output DIO1 001 = Output DIO2 010 = Output DIO3 011 = Input to WM8593 100 = Output DIO5 101 = Output GPIO1 110 = Output GPIO2 111 = Output ADC Data Output
6:4
WORD CLK4_ SEL[2:0]
011
9:7
DIO4_ SEL[2:0]
011
Table 35 Digital Audio Port 4 Pin Configuration
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Product Preview The MCLK5 and DIO5 pins are defined individually as an input or an output using MCLK5_SEL[2:0] and DIO5_SEL[2:0] respectively. The BCLK5 and LRCLK5 pins are always defined as inputs or outputs together using WORDCLK5_SEL[2:0].
REGISTER ADDRESS R41 AIF_MUX5 29h
BIT 3:1
LABEL MCLK5_ SEL[2:0]
DEFAULT 100
DESCRIPTION MCLK5 Pin Function Select 000 = Output MCLK1 001 = Output MCLK2 010 = Output MCLK3 011 = Output MCLK4 100 = Input to WM8593 101 to 111 = Reserved BCLK5 and LRCLK5 Pins Function Select 000 = Output BCLK1 and LRCLK1 001 = Output BCLK2 and LRCLK2 010 = Output BCLK3 and LRCLK3 011 = Output BCLK4 and LRCLK4 100 = Inputs to WM8593 101 = Output DAC1BCLK and DAC1LRCLK (when DAC1 is in master mode) 110 = Output DAC2BCLK and DAC2LRCLK (when DAC2 is in master mode) 111 = Output ADCBCLK and ADCBCLK (when ADC is master mode) DIO5 Pin Function Select 000 = Output DIO1 001 = Output DIO2 010 = Output DIO3 011 = Output DIO4 100 = Input to WM8593 101 = Output GPIO1 110 = Output GPIO2 111 = Output ADC Data Output
6:4
WORD CLK5_ SEL[2:0]
100
9:7
DIO5_ SEL[2:0]
100
Table 36 Digital Audio Port 5 Pin Configuration
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WM8593
ADC AUDIO INTERFACE CLOCK CONFIGURATION
The WM8593 ADC has an independent audio interface which can be configured to select the required signals from any of the digital audio ports. The audio interface is not restricted to take each signal from the same digital audio port, although the BCLK and LRCLK signals are selected together. For example, it is possible to use MCLK1, BCLK2, LRCLK2 and DIO5 as the digital audio port pins that connect to the ADC audio interface through the audio interface mux if required. The MCLK is always an input to the ADC audio interface is selected using ADCMCLK_SEL[2:0]. The BCLK and LRCLK are always selected together, and can be either an input to the ADC audio interface (when the ADC is in slave mode) or an output from the ADC audio interface (when the ADC is in master mode). BCLK and LRCLK are selected using ADCWORDCLK_SEL[2:0]. REGISTER ADDRESS R44 AIF_MUX8 2Ch BIT 3:1 LABEL ADC MCLK_ SEL[2:0] DEFAULT 000 DESCRIPTION ADCMCLK Select 000 = Use MCLK1 001 = Use MCLK2 010 = Use MCLK3 011 = Use MCLK4 100 = Use MCLK5 101 to 111 = Reserved ADC BCLK and LRCLK Select 000 = Use BCLK1 and LRCLK1 001 = Use BCLK2 and LRCLK2 010 = Use BCLK3 and LRCLK3 011 = Use BCLK4 and LRCLK4 100 = Use BCLK5 and LRCLK5 101 = Use DAC1BCLK and DAC1LRCLK (when DAC1 is in master mode) 110 = Use DAC2BCLK and DAC2LRCLK (when DAC2 is in master mode) 111 = Output ADCBCLK and ADCBCLK (when ADC is master mode)
6:4
ADC WORD CLK_ SEL[2:0]
000
Table 37 ADC Audio Interface Clock Configuration
DAC1 AND DAC2 AUDIO INTERFACE CLOCK CONFIGURATION
Both DACs on the WM8593 have independent audio interfaces which can be configured to select the required signals from any of the digital audio ports. The audio interfaces are not restricted to take each signal from the same digital audio ports, although the BCLK and LRCLK signals are selected together. For example, it is possible to use MCLK1, BCLK2, LRCLK2 and DIO5 as the digital audio port pins that connect to the DAC1 audio interface through the audio interface mux, while using MCLK2, BCLK1, LRCLK1 and DIO3 for DAC2 if required. DAC1MCLK and DAC2MCLK are always inputs to the DAC1 and DAC2 audio interfaces and are selected using DAC1MCLK_SEL[2:0] and DAC2MCLK_SEL[2:0] respectively. DAC1BCLK and DAC1LRCLK are always selected together, and can be either an input to the DAC1 audio interface (when DAC1 is in slave mode) or an output from the DAC1 audio interface (when DAC1 is in master mode). DAC2BCLK and DAC2LRCLK are always selected together, and can be either an input to the DAC2 audio interface (when DAC2 is in slave mode) or an output from the DAC2 audio interface (when DAC2 is in master mode). DAC1BCLK and DAC1LRCLK are selected using DAC1WORDCLK_SEL[2:0], while DAC2BCLK and DAC2LRCLK are selected using DAC2WORDCLK_SEL[2:0]. Finally, the data input to the DAC1 audio interface is configured using DAC1DIN_SEL[2:0] and the data input to the DAC2 audio interface is configured using DAC2DIN_SEL[2:0]
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REGISTER ADDRESS R42 AIF_MUX6 2Ah R43 AIF_MUX7 2Bh R42 AIF_MUX6 2Ah 6:4 BIT 3:1 LABEL DAC1 MCLK_ SEL[2:0] DAC2 MCLK_ SEL[2:0] DAC1 WORD CLK_ SEL[2:0] 001 DEFAULT 001
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DESCRIPTION DAC MCLK Select 000 = Use MCLK1 001 = Use MCLK2 010 = Use MCLK3 011 = Use MCLK4 100 = Use MCLK5 101 to 111 = Reserved DAC BCLK and DAC LRCLK Select 000 = Use BCLK1 and LRCLK1 001 = Use BCLK2 and LRCLK2 010 = Use BCLK3 and LRCLK3 011 = Use BCLK4 and LRCLK4 100 = Use BCLK5 and LRCLK5 101 = Use DAC1BCLK and DAC1LRCLK (when DAC1 is in master mode) 110 = Use DAC2BCLK and DAC2LRCLK (when DAC2 is in master mode) 111 = Use ADCBCLK and ADCBCLK (when ADC is master mode) DAC DIN Select 000 = Use DIO1 001 = Use DIO2 010 = Use DIO3 011 = Use DIO4 100 = Use DIO5 101 = Use GPIO1 110 = Use GPIO2 111 = Use ADCDOUT
R43 AIF_MUX7 2Bh
DAC2 WORD CLK_ SEL[2:0]
R42 AIF_MUX6 2Ah
9:7
DAC1 DIN_ SEL[2:0]
001
R43 AIF_MUX7 2Bh
DAC2 DIN_ SEL[2:0]
Table 38 DAC1 and DAC2 Audio Interface Clock Configuration
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WM8593
UPDATE FUNCTION
To prevent clock contention issues during setup of the digital audio interface mux, an update system has been implemented. This allows the registers to be configured as required and the update to be applied with the last register write synchronise the configuration of the digital audio mux. An update can be generated using any of the update bits shown in Table 39. REGISTER ADDRESS R37 AIF_MUX1 25h R38 AIF_MUX2 26h R39 AIF_MUX3 27h R40 AIF_MUX4 28h R41 AIF_MUX5 29h R42 AIF_MUX6 2Ah R43 AIF_MUX7 2Bh R44 AIF_MUX8 2Ch BIT 10 LABEL PORT1_ UPD PORT2_ UPD PORT3_ UPD PORT4_ UPD PORT5_ UPD DAC1_ UPD DAC2_ UPD ADC_ UPD DEFAULT 0 DESCRIPTION Update 0 = Latch corresponding settings into Register Map but do not update 1 = Latch corresponding settings into Register Map and update all simultaneously
10
10
10
10
10
10
10
Table 39 Audio Interface Mux Update Bits
DETAILS ON CLOCK SWITCHING
In order to avoid short clock pulses (glitches) when switching between two independent clock sources, the MCLK and BCLK switching is carefully controlled within the WM8593 using various feedback and logic mechanisms. This controlled switching applies to all MCLK and BCLK digital audio port pins, and also when switching MCLK and BCLK sources in the ADC, DAC1 and DAC2 audio interfaces. Example: Switching from MCLK2 to MCLK3 using the MCLK4 pin CLK_A is applied to the MCLK2 pin, and CLK_B is applied to the MCLK3 pin. Initially, MCLK4_SEL[2:0]=001, so CLK_A is output on the MCLK4 pin. To change the output clock to CLK_B, set MCLK4_SEL[2:0]=010. The logic waits until CLK_A (MCLK2 pin) is low then disconnects CLK_A from the output (MCLK4) pin. The output pin (MCLK4) now outputs logic 0 for two rising edges of CLK_B (MCLK3 pin) before starting to output CLK_B. This behaviour is shown in Figure 23:
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Figure 23 Clock Switching Example If CLK_A in the previous example is not running the logic that controls switching between clocks will not function. In this case, it is possible to force an update on any individual digital audio port or audio interface using the relevant force bit. If this functionality is required, the relevant force bit should be set to `1' and then set back to `0' again. Example: Switching from MCLK2 to MCLK3 using the MCLK4 pin when MCLK2 is not present CLK_A is applied to the MCLK2 pin, and CLK_B is applied to the MCLK3 pin. Initially, MCLK4_SEL[2:0]=001, so CLK_A is output on the MCLK4 pin. However, CLK_A is not running. To change the output clock to CLK_B, set MCLK4_SEL[2:0]=010 and PORT4_FORCE=1. Finally, set PORT4_FORCE=0 to complete the switch. REGISTER ADDRESS R37 AIF_MUX1 25h R38 AIF_MUX2 26h R39 AIF_MUX3 27h R40 AIF_MUX4 28h R41 AIF_MUX5 29h R42 AIF_MUX6 2Ah R43 AIF_MUX7 2Bh R44 AIF_MUX8 2Ch BIT 0 LABEL PORT1_ FORCE PORT2_ FORCE PORT3_ FORCE PORT4_ FORCE PORT5_ FORCE DAC1_ FORCE DAC2_ FORCE ADC_ FORCE DEFAULT 0 DESCRIPTION Force Clocks to Change 0 = Wait until clocks are safe before switching between clock sources 1 = Force clock sources to change immediately Note: These bits must be returned to `0' before clocks will be output
0
0
0
0
0
0
0
Table 40 Audio Interface Mux Force Bits
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WM8593
USING GPIO PINS AS ADDITIONAL DATA PINS
There are two GPIO pins, GPIO1 and GPIO2, which can be used as additional pins to connect to external devices. GPIO1 is controlled by GPIO1_SEL[2:0] and GPIO2 by GPIO2_SEL[2:0]. REGISTER ADDRESS R45 AIF_MUX9 2Dh BIT 3:1 LABEL GPIO1_ SEL[2:0] DEFAULT 000 DESCRIPTION GPIO1 Pin Function Select 000 = Source DIO1 001 = Source DIO2 010 = Source DIO3 011 = Source DIO4 100 = Source DIO5 101 = Input to WM8593 110 = Source GPIO2 111 = Source ADC Data Output GPIO1 Update 0 = Latch corresponding GPIO1 settings into Register Map but do not update 1 = Latch corresponding GPIO1 settings into Register Map and update
10
GPIO1_ UPD
0
Table 41 GPIO1 Audio Interface Mux Configuration REGISTER ADDRESS R46 AIF_MUX10 2Eh BIT 3:1 LABEL GPIO2_ SEL[2:0] DEFAULT 000 DESCRIPTION GPIO2 Pin Function Select 000 = Source DIO1 001 = Source DIO2 010 = Source DIO3 011 = Source DIO4 100 = Source DIO5 101 = Source GPIO1 110 = Input to WM8593 111 = Source ADC Data Output GPIO2 Update 0 = Latch corresponding GPIO2 settings into Register Map but do not update 1 = Latch corresponding GPIO2 settings into Register Map and update
10
GPIO2_ UPD
0
Table 42 GPIO2 Audio Interface Mux Configuration
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JACK DETECT
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When using the WM8593 with headphones, a jack detect function is available using the GPIO pins. The jack detect function is controlled using GPIO1_APP and GPIO2_APP. The polarity of the jack detect signal can be inverted using JD_INV. When a jack is detected, the WM8593 will automatically mute PGAs as defined by JD_PGA1L_MUTE, JD_PGA1R_MUTE, JD_PGA2L_MUTE, JD_PGA2R_MUTE, JD_PGA3L_MUTE and JD_PGA3R_MUTE. See Application Information section for details of connections to the headphone jack. Example: Mute speakers when headphone is inserted Assume PGA1L is connected to VOUT1L, PGA1R is connected to VOUT1R and so on. VOUT1L and VOUT1R are used to drive the speaker amplifier, and VOUT3L and VOUT3R are used to drive headphones directly. Set GPIO1_APP=1 to enable jack detect on GPIO1, then set JD_PGA1L_MUTE=1 and JD_PGA1R_MUTE=1 to mute PGA1L and PGA1R when a set of headphones is inserted. REGISTER ADDRESS R27 GEN 1Bh BIT 0 LABEL GPIO1_ APP DEFAULT 0 DESCRIPTION GPIO1 Application Select 0 = Use GPIO1 as data pin for audio interface mux 1 = Use GPIO1 as input for jack detect GPIO2 Application Select 0 = Use GPIO2 as data pin for audio interface mux 1 = Use GPIO2 as input for jack detect Jack Detect Polarity 0 = Normal (active low) 1 = Inverted (active high) Jack Detect Mute Control 0 = Do not mute PGA when jack is detected 1 = Mute PGA when jack is detected
1
GPIO2_ APP
0
2
JD_INV
0
R26 PGA_CTRL2 1Ah
7
JD_ PGA1L_ MUTE JD_ PGA1R_ MUTE JD_ PGA2L_ MUTE JD_ PGA2R_ MUTE JD_ PGA3L_ MUTE JD_ PGA3R_ MUTE
0
8
0
9
0
10
0
11
0
12
0
Table 43 Jack Detect Control
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WM8593
POP AND CLICK PERFORMANCE
The WM8593 includes a number of features designed to minimise pops and clicks in various phases of operation including power up, power down, changing analogue paths and starting/stopping clocks. In order to ensure optimum performance, the following sequences should be followed.
POWERUP SEQUENCE
1. 2. Apply power to the WM8593 (see Power On Reset). Set-up initial internal biases: * * * 3. SOFT_ST=1 FAST_EN=1 POBCTRL=1
Enable output drivers to allow the AC coupling capacitors at the output stage to be precharged to DACVMID: * * VOUTxL_EN=1 VOUTxR_EN=1
4.
Enable DACVMID. 500k selected here for optimum pop reduction: * VMID_SEL=10
5.
Wait until DACVMID has fully charged. The time is dependent on the capacitor values used to AC-couple the outputs and to decouple DACVMID, and the VMID_SEL value chosen. An approximate delay of 6xRCms can be used, where R is the DACVMID resistance and C is the decoupling capacitor on DACVMID. For DACVMID resistance of 50k and C=4.7uF, the delay should be approximately 1.5 seconds. * Insert delay
6.
Enable the master bias and DACVMID buffer: * * BIAS_EN=1 BUFIO_EN=1
7.
Switch the output drivers to use the master bias instead of the power up (fast) bias: * POBCTRL=0
8.
Enable all functions (DACs, ADC, PGAs) required for use. Outputs are muted by default so the write order is not important. Unmute the outputs and switch DACVMID resistance to 50k for normal operation: * * * VOUTxL_MUTE=0 VOUTxR_MUTE=0 VMID_SEL=01
9.
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WM8593
POWERDOWN SEQUENCE
1. Mute all outputs: * 2. MUTE_ALL=1
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Set up biases for power down mode: * * * * * * FAST_EN=1 VMID_SEL=01 BIAS_EN=1 BUFIO_EN=1 VMIDTOG=1 SOFT_ST=0
3.
Switch outputs to use fast bias instead of master bias: * POBCTRL=1
4.
Power down all WM8593 functions (ADC, DACs, PGAs etc.). The outputs are muted so the write order is not important. Power down VMID to allow the analogue outputs to ramp gently to ground in a pop-free manner. * VMID_SEL=00
5.
6.
Wait until DACVMID has fully discharged. The time taken depends on system capacitance. * Insert delay
7.
Clamp outputs to ground. * APE_B=0
8.
Power down outputs. * * VOUTxL_EN=0 VOUTxR_EN=0
9.
Disable remaining bias control bits. * * * FAST_EN=0 POBCTRL=0 BIAS_EN=0
Power supplies can now be safely removed from the WM8593 if desired. Table 44 describes the various bias control bits for power up/down control.
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WM8593
REGISTER ADDRESS R35 BIAS 23h
BIT 0
LABEL POBCTRL
DEFAULT 0
DESCRIPTION Bias Source for Output Amplifiers 0 = Output amplifiers use master bias 1 = Output amplifiers use fast bias VMID Power Down Characteristic 0 = Slow ramp 1 = Fast ramp Fast Bias Enable 0 = Fast bias disabled 1 = Fast bias enabled VMID Buffer Enable 0 = VMID Buffer disabled 1 = VMID Buffer enabled VMID Soft Ramp Enable 0 = Soft ramp disabled 1 = Soft ramp enabled Master Bias Enable 0 = Master bias disabled 1 = Master bias enabled Also powers down ADCVMID VMID Resistor String Value Selection (DACVMID only) 00 = off (no VMID) 01 = 100k 10 = 500k 11 = 10k The selection is the total resistance of the string from DACREFP to DACREFN. The ADCVMID resistance is fixed at 200k.
1
VMIDTOG
0
2
FAST_EN
0
3
BUFIO_ EN SOFT_ST
0
4
1
5
BIAS_EN
0
7:6
VMID_ SEL[1:0]
00
Table 44 Bias Control
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WM8593 REGISTER MAP
Dec Addr 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 9 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Hex Addr Name 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 1 0 1 1 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 A 1 B 1 C 1 D 1 E 1 F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E DEVICE_ID REVISION DAC1 _CTRL1 DAC1 _CTRL2 DAC1 _CTRL3 DAC1 L_VOL DAC1 R_VOL DAC2_CTRL1 DAC2_CTRL2 DAC2_CTRL3 DAC2L_VOL DAC2R_VOL ENABLE ADC_CTRL1 ADC_CTRL2 ADC_CTRL3 ADCL_VOL ADCR_VOL PGA1 L_VOL PGA1 R_VOL PGA2L_VOL PGA2R_VOL PG3L_VOL PGA3R_VOL PGA_CTRL1 PGA_CTRL2 GEN INPUT_CTRL1 INPUT_CTRL2 INPUT_CTRL3 INPUT_CTRL4 OUTPUT_CTRL1 OUTPUT_CTRL2 OUTPUT_CTRL3 BIAS PGA_CTRL_3 AIF_MUX1 AIF_MUX2 AIF_MUX3 AIF_MUX4 AIF_MUX5 AIF_MUX6 AIF_MUX7 AIF_MUX8 AIF_MUX9 AIF_MUX1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_ZC_EN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_HPD 0 0 0 0 0 0 0 0 0 0 0
JD_PGA3R_M UTE
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15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Hex Default 0x8594
Read: DEVICE_ID[1 5:0] / Write: SW_RST 0 0 0 DAC1 _MUTE 0 0 0 0 DAC2_MUTE 0 0 0 0 0 ADCL_INV 0 0 0 0 0 0 0 0 0 0 0
JD_PGA2 L_M UTE
0 DAC1 _EN 0 0 DAC1 L_VU DAC1 R_VU DAC2_EN 0 0 DAC2L_VU DAC2R_VU 0 ADCR_INV 0 0 ADCL_VU ADCR_VU PGA1 L_VU PGA1 R_VU PGA2L_VU PGA2R_VU PGA3L_VU PGA3R_VU 0
JD_PGA1R_M UTE
REVNUM[7:0] DAC1 _ZCEN 0 0 DAC1 _DEEMPH 0 0 0 DAC1 _LRP DAC1 _BCP DAC1 _BCLKDIV[2:0] 0 DAC1 L_VOL[7:0] DAC1 R_VOL[7:0] DAC2_ZCEN 0 0 DAC2_DEEMPH 0 0 0 DAC2_LRP DAC2_BCP DAC2_BCLKDIV[2:0] 0 DAC2L_VOL[7:0] DAC2R_VOL[7:0] 0 ADC_LRSWAP 0 0 0 0 0 ADC_EN 0 ADC_LRP 0 ADC_BCP ADC_BCLKDIV[2:0] 0 ADCL_VOL[7:0] ADCR_VOL[7:0] PGA1 L_VOL[7:0] PGA1 R_VOL[7:0] PGA2L_VOL[7:0] PGA2R_VOL7:0] PGA3L_VOL[7:0] PGA3R_VOL[7:0] PGA3R_ZC
JD_PGA1L_M UTE
0x0000 DAC1 _WL[1 :0] DAC1 _FMT[1 :0] DAC1 _SR[2:0] 0 0 0 DAC1 _MSTR 0x008A 0x0000 0x0000 0x00C8 0x00C8 DAC2_WL[1 :0] DAC2_FMT[1 :0] DAC2_SR[2:0] 0 0 0 DAC2_MSTR 0x008A 0x0000 0x0000 0x00C8 0x00C8 0 ADC_WL[1 :0] 0 0 GLOBAL_EN ADC_FMT[1 :0] ADC_SR[2:0] 0 0 ADC_MSTR 0x0000 0x200A 0x0000 0x0000 0x00C3 0x00C3 0x000C 0x000C 0x000C 0x000C 0x000C 0x000C PGA1 L_ZC VOUT1 R_MUTE JD_INV ATTACK_BYPASSDECAY_BYPASS VOUT1 L_MUTE GPIO2_APP MUTE_ALL GPIO1 _APP 0x00FC 0x007E 0x0048 0x0000 0x0000 0x0008 PGA1 L_EN 0x0000 0x0088 0x01 63 VOUT1 L_TRI POBCTRL PGA_SAFE_SW PORT1 _FORCE PORT2_FORCE PORT3_FORCE PORT4_FORCE PORT5_FORCE DAC1 _FORCE DAC2_FORCE ADC_FORCE 0 0 0x0040 0x001 0 0x0002 0x0000 0x0092 0x01 24 0x01 B6 0x0248 0x0092 0x0092 0x0248 0x0000 0x0000
DAC1 _OP_MUX[1 :0] 0 0 0 0 0 0 0 0
DAC2_OP_MUX[1 :0] 0 0 0 0 0 0 0 0 0 0
ADC_DATA_SEL[1 :0] 0 0 0 0 0 0 0 0 0 0 0
JD_PGA3 L_M UTE
0 0 0 0 0 0 0 0 0 0 0
JD_PGA2R_M UTE
PGA3L_ZC VOUT3R_MUTE
PGA2R_ZC VOUT3L_MUTE PGA_SR[2:0]
PGA2L_ZC VOUT2R_MUTE
PGA1 R_ZC VOUT2L_MUTE AUTO_INC
0 0 0 0 0 0 0 VOUT3R_EN 0 0 0 0 0 0 0 0 0 0 0 0
0
0
0
0
0
PGA2L_IN_SEL[3:0] PGA3R_IN_SEL[3:0] 0 0 0 0 VOUT3L_EN 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SWITCH_EN 0 0 0 VOUT2R_EN 0 PGA_UPD PORT1 _UPD PORT2_UPD PORT3_UPD PORT4_UPD PORT5_UPD DAC1 _UPD DAC2_UPD ADC_UPD GPIO1 _UPD GPIO2_UPD 0 0 ADC_AMP_VOL[1 :0] 0 0 0 VOUT2L_EN 0 0 VOUT1 R_EN 0 0 DIO1 _SEL[2:0] DIO2_SEL[2:0] DIO3_SEL[2:0] DIO4_SEL[2:0] DIO5_SEL[2:0] DAC1 DIN_SEL[2:0] DAC2DIN_SEL[2:0] ADCDOUT_SEL[2:0] 0 0 0 0 0 0
PGA1 R_IN_SEL[3:0] PGA3L_IN_SEL[3:0] ADCR_SEL[3:0] ADCR_AMP_EN ADCL_AMP_EN VOUT2L_SEL[2:0] VOUT3R_SEL[2:0] VOUT1 L_EN APE_B VOUT3R_TRI BIAS_EN 0 0 WORDCLK1 _SEL[2:0] WORDCLK2_SEL[2:0] WORDCLK3_SEL[2:0] WORDCLK4_SEL[2:0] WORDCLK5_SEL[2:0] DAC1 WORDCLK_SEL[2:0] DAC2WORDCLK_SEL[2:0] ADCWORDCLK_SEL[2:0] 0 0 0 0 0 0 PGA3R_EN PGA3L_EN VOUT1 R_SEL[2:0] VOUT3L_SEL[2:0] VOUT3L_TRI SOFT_ST 0 VOUT2R_TRI BUFIOEN PGA2R_EN
PGA1 L_IN_SEL[3:0] PGA2R_IN_SEL[3:0] ADCL_SEL[3:0] PGA2L_EN PGA1 R_EN VOUT1 L_SEL[2:0] VOUT2R_SEL[2:0] VOUT2L_TRI FAST_EN PGA_SEL[2:0] MCLK1 _SEL[2:0] MCLK2_SEL[2:0] MCLK3_SEL[2:0] MCLK4_SEL[2:0] MCLK5_SEL[2:0] DAC1 MCLK_SEL[2:0] DAC2MCLK_SEL[2:0] ADCMCLK_SEL[2:0] GPIO1 _SEL[2:0] GPIO2_SEL[2:0] VOUT1 R_TRI VMIDTOG
VMID_SEL[1 :0]
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WM8593
R0 (0h) - Software Reset / Device ID Register (DEVICE_ID) Bit # Read Write Default Bit # Read Write Default Function DEVICEID[15:0] SW_RST 1 0 0 1 1 7 0 6 0 5 0 4 SW_RST 0 Description Device ID A read of this register will return the device ID. In this case 0x8593. Software Reset A write of any value to this register will generate a software reset. 1 0 0 N/A = Not Applicable (no function implemented) 15 14 13 12 SW_RST 0 3 1 2 0 1 1 0 11 10 9 8 DEVICE_ID[15:8]
DEVICE_ID[7:0]
Figure 24 R0 - Software Reset / Device ID
R1 (01h) - Device Revision Register (REVISION) Bit # Read Write Default Bit # Read Write Default Function REVNUM[7:0] N/A N/A N/A 15 0 N/A 0 7 14 0 N/A 0 6 13 0 N/A 0 5 12 0 N/A 0 4 N/A 11 0 N/A 0 3 N/A Description Device Revision A read of this register will return the device revision number. This number is sequentially incremented if the device design is updated. 10 0 N/A 0 2 N/A 9 0 N/A 0 1 N/A 8 0 N/A 0 0 N/A -
REVNUM[7:0]
N/A = Not Applicable (no function implemented)
Figure 25 R1 - Device Revision Register
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WM8593
R2 (02h) - DAC Control Register 1 (DAC1_CTRL1) Bit # Read Write Default Bit # Read Write Default Function DAC1_FMT[1:0] DAC1 Audio Interface Format 00 = Right Justified 01 = Left Justified 10 = I2S 11 = DSP DAC1 Audio Interface Word Length 00 = 16-bit 01 = 20-bit 10 = 24-bit 11 = 32-bit (not available in Right Justified mode) DAC1 BCLK Polarity 0 = DACBCLK not inverted - data latched on rising edge of BCLK 1 = DACBCLK inverted - data latched on falling edge of BCLK DAC1 LRCLK Polarity 0 = DACLRCLK not inverted 1 = DACLRCLK inverted DAC1 Deemphasis 0 = No deemphasis 1 = Apply 44.1kHz deemphasis DAC1 Digital Volume Control Zero Cross Enable 0 = Do not use zero cross 1 = Use zero cross DAC1 Enable 0 = DAC disabled 1 = DAC enabled DAC1 Softmute 0 = Normal operation 1 = Softmute applied DAC1 Digital Monomix 00 = Stereo (Normal Operation) 01 = Mono (Left data to DAC1R) 10 = Mono (Right data to DAC1L) 11 = Digital Monomix, (L+R)/2 15 0 N/A 0 7 DAC1_ZCEN 1 14 0 N/A 0 6 DAC1_ DEEMPH 0 13 0 N/A 0 5 DAC1_LRP 0 12 0 N/A 0 4 DAC1_BCP 0 11 10 9
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8 DAC1_EN 0 0
DAC1_OP_MUX[1:0] 0 3 0 2
DAC1_MUTE 0 1
DAC1_WL[1:0] 1 Description 0
DAC1_FMT[1:0] 1 0
N/A = Not Applicable (no function implemented)
DAC1_WL[1:0]
DAC1_BCP
DAC1_LRP
DAC1_DEEMPH
DAC1_ZCEN
DAC1_EN
DAC1_MUTE
DAC1_OP_MUX[1:0]
Figure 26 R2 - DAC1 Control Register 1
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WM8593
R3 (03h) - DAC1 Control Register 2 (DAC1_CTRL2) Bit # Read Write Default Bit # Read Write Default Function DAC1_SR[2:0] DAC1 MCLK:LRCLK Ratio 000 = Auto detect 001 = 128fs 010 = 192fs 011 = 256fs 100 = 384fs 101 = 512fs 110 = 768fs 111 = 1152fs DAC1 BCLK Rate 000 = MCLK / 4 001 = MCLK / 8 010 = 32fs 011 = 64fs 100 = 128fs All other values of DAC1_BCLKDIV[2:0] are reserved 15 0 N/A 0 7 0 N/A 0 14 0 N/A 0 6 0 N/A 0 0 13 0 N/A 0 5 12 0 N/A 0 4 DAC1_BCLKDIV[2:0] 0 0 Description 0 11 0 N/A 0 3 10 0 N/A 0 2 9 0 N/A 0 1 DAC1_SR[2:0] 0 0 8 0 N/A 0 0
N/A = Not Applicable (no function implemented)
DAC1_ BCLKDIV [2:0]
Figure 27 R3 - DAC1 Control Register 2
R4 (04h) - DAC1 Control Register 3 (DAC1_CTRL3) Bit # Read Write Default Bit # Read Write Default Function DAC1_MSTR 15 0 N/A 0 7 0 N/A 0 14 0 N/A 0 6 0 N/A 0 13 0 N/A 0 5 0 N/A 0 12 0 N/A 0 4 0 N/A 0 11 0 N/A 0 3 0 N/A 0 Description DAC1 Master Mode Select 0 = Slave mode, DACBCLK1 and DACLRCLK1 are inputs to WM8593 1 = Master mode, DACBCLK1 and DACLRCLK1 are outputs from WM8593 10 0 N/A 0 2 0 N/A 0 9 0 N/A 0 1 0 N/A 0 8 0 N/A 0 0 DAC1_MSTR 0
N/A = Not Applicable (no function implemented)
Figure 28 R4 - DAC1 Control Register 3
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WM8593
R5 (05h) - DAC1L Digital Volume Control Register (DAC1L_VOL) Bit # Read Write Default Bit # Read Write Default Function DAC1L_VOL[7:0] DAC1L Digital Volume 0000 0000 = -100dB 0000 0001 = -99.5dB 0000 0010 = -99dB ...0.5dB steps 1100 1000 = 0dB ...0.5dB steps 1101 1111 = +11.5dB 111X XXXX = +12dB 1 1 0 15 0 N/A 0 7 14 0 N/A 0 6 13 0 N/A 0 5 12 0 N/A 0 4 11 0 N/A 0 3 10 0 N/A 0 2 9 0 N/A 0 1
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8 DAC1L_VU 0 0
DAC1L_VOL[7:0] 0 1 Description 0 0 0
N/A = Not Applicable (no function implemented)
DAC1L_VU
DAC1L Digital Volume Update 0 = Latch DAC1L_VOL[7:0] into Register Map but do not update volume 1 = Latch DAC1L_VOL[7:0] into Register Map and update left and right channels simultaneously
Figure 29 R5 - DAC1L Digital Volume Control Register R6 (06h) - DAC1R Digital Volume Control Register (DAC1R_VOL) Bit # Read Write Default Bit # Read Write Default Function DAC1R_VOL[7:0] DAC1R Digital Volume 0000 0000 = -100dB 0000 0001 = -99.5dB 0000 0010 = -99dB ...0.5dB steps 1100 1000 = 0dB ...0.5dB steps 1101 1111 = +11.5dB 111X XXXX = +12dB DAC1R Digital Volume Update 0 = Latch DACR_VOL[7:0] into Register Map but do not update volume 1 = Latch DACR_VOL[7:0] into Register Map and update left and right channels simultaneously 1 1 0 15 0 N/A 0 7 14 0 N/A 0 6 13 0 N/A 0 5 12 0 N/A 0 4 11 0 N/A 0 3 10 0 N/A 0 2 9 0 N/A 0 1 8 DAC1R_VU 0 0
DAC1R_VOL[7:0] 0 1 Description 0 0 0
N/A = Not Applicable (no function implemented)
DAC1R_VU
Figure 30 R6 - DAC1R Digital Volume Control Register
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WM8593
R7 (07h) - DAC2 Control Register 1 (DAC2_CTRL1) Bit # Read Write Default Bit # Read Write Default Function DAC2_FMT[1:0] DAC2 Audio Interface Format 00 = Right Justified 01 = Left Justified 10 = I2S 11 = DSP DAC2 Audio Interface Word Length 00 = 16-bit 01 = 20-bit 10 = 24-bit 11 = 32-bit (not available in Right Justified mode) DAC2 BCLK Polarity 0 = DACBCLK not inverted - data latched on rising edge of BCLK 1 = DACBCLK inverted - data latched on falling edge of BCLK DAC2 LRCLK Polarity 0 = DACLRCLK not inverted 1 = DACLRCLK inverted DAC2 Deemphasis 0 = No deemphasis 1 = Apply 44.1kHz deemphasis DAC2 Digital Volume Control Zero Cross Enable 0 = Do not use zero cross 1 = Use zero cross DAC2 Enable 0 = DAC2 disabled 1 = DAC2 enabled DAC2 Softmute 0 = Normal operation 1 = Softmute applied DAC2 Digital Monomix 00 = Stereo (Normal Operation) 01 = Mono (Left data to Right DAC2) 10 = Mono (Right data to Left DAC2) 11 = Digital Monomix, (L+R)/2 15 0 N/A 0 7 DAC2_ZCEN 1 14 0 N/A 0 6 DAC2_ DEEMPH 0 13 0 N/A 0 5 DAC2_LRP 0 12 0 N/A 0 4 DAC2_BCP 0 11 10 9 DAC2_MUTE 0 1 8 DAC2_EN 0 0
DAC2_OP_MUX[1:0] 0 3 0 2
DAC2_WL[1:0] 1 Description 0
DAC2_FMT[1:0] 1 0
N/A = Not Applicable (no function implemented)
DAC2_WL[1:0]
DAC2_BCP
DAC2_LRP
DAC2_DEEMPH
DAC2_ZCEN
DAC2_EN
DAC2_MUTE
DAC2_OP_MUX[1:0]
Figure 31 R7 - DAC2 Control Register 1
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WM8593
R8 (08h) - DAC2 Control Register 2 (DAC2_CTRL2) Bit # Read Write Default Bit # Read Write Default Function DAC2_SR[2:0] DAC2 MCLK:LRCLK Ratio 000 = Auto detect 001 = 128fs 010 = 192fs 011 = 256fs 100 = 384fs 101 = 512fs 110 = 768fs 111 = 1152fs DAC2 BCLK Rate 000 = MCLK / 4 001 = MCLK / 8 010 = 32fs 011 = 64fs 100 = 128fs All other values of DAC2_BCLKDIV[2:0] are reserved 15 0 N/A 0 7 0 N/A 0 14 0 N/A 0 6 0 N/A 0 0 13 0 N/A 0 5 12 0 N/A 0 4 DAC2_BCLKDIV[2:0] 0 0 Description 0 11 0 N/A 0 3 10 0 N/A 0 2 9 0 N/A 0 1
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8 0 N/A 0 0
DAC2_SR[2:0] 0 0
N/A = Not Applicable (no function implemented)
DAC2_BCLKDIV[2:0]
Figure 32 R8 - DAC2 Control Register 2 R9 (09h) - DAC2 Control Register 3 (DAC2_CTRL3) Bit # Read Write Default Bit # Read Write Default Function DAC2_MSTR 15 0 N/A 0 7 0 N/A 0 14 0 N/A 0 6 0 N/A 0 13 0 N/A 0 5 0 N/A 0 12 0 N/A 0 4 0 N/A 0 11 0 N/A 0 3 0 N/A 0 Description DAC2 Master Mode Select 0 = Slave mode, DACBCLK2 and DACLRCLK2 are inputs to WM8593 1 = Master mode, DACBCLK2 and DACLRCLK2 are outputs from WM8593 10 0 N/A 0 2 0 N/A 0 9 0 N/A 0 1 0 N/A 0 8 0 N/A 0 0 DAC2_MSTR 0
N/A = Not Applicable (no function implemented)
Figure 33 R9 - DAC2 Control Register 3
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WM8593
R10 (0Ah) - DAC2L Digital Volume Control Register (DAC2L_VOL) Bit # Read Write Default Bit # Read Write Default Function DAC2L_VOL[7:0] DAC2 Digital Volume 0000 0000 = -100dB 0000 0001 = -99.5dB 0000 0010 = -99dB ...0.5dB steps 1100 1000 = 0dB ...0.5dB steps 1101 1111 = +11.5dB 111X XXXX = +12dB DAC2 Digital Volume Update 0 = Latch DAC2L_VOL[7:0] into Register Map but do not update volume 1 = Latch DAC2L_VOL[7:0] into Register Map and update left and right channels simultaneously 1 1 0 15 0 N/A 0 7 14 0 N/A 0 6 13 0 N/A 0 5 12 0 N/A 0 4 11 0 N/A 0 3 10 0 N/A 0 2 9 0 N/A 0 1 8 DAC2L_VU 0 0
DAC2L_VOL[7:0] 0 1 Description 0 0 0
N/A = Not Applicable (no function implemented)
DAC2L_VU
Figure 34 R10 - DAC2L Digital Volume Control Register R11 (0Bh) - DAC2R Digital Volume Control Register (DAC2R_VOL) Bit # Read Write Default Bit # Read Write Default Function DAC2R_VOL[7:0] DAC2R Digital Volume 0000 0000 = -100dB 0000 0001 = -99.5dB 0000 0010 = -99dB ...0.5dB steps 1100 1000 = 0dB ...0.5dB steps 1101 1111 = +11.5dB 111X XXXX = +12dB DAC2R Digital Volume Update 0 = Latch DAC2R_VOL[7:0] into Register Map but do not update volume 1 = Latch DAC2R_VOL[7:0] into Register Map and update left and right channels simultaneously 1 1 0 15 0 N/A 0 7 14 0 N/A 0 6 13 0 N/A 0 5 12 0 N/A 0 4 11 0 N/A 0 3 10 0 N/A 0 2 9 0 N/A 0 1 8 DAC2R_VU 0 0
DAC2R_VOL[7:0] 0 1 Description 0 0 0
N/A = Not Applicable (no function implemented)
DAC2R_VU
Figure 35 R11 - DAC2R Digital Volume Control Register
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WM8593
R12 (0Ch) - Device Enable Register (ENABLE) Bit # Read Write Default Bit # Read Write Default Function GLOBAL_EN 15 0 N/A 0 7 0 N/A 0 14 0 N/A 0 6 0 N/A 0 13 0 N/A 0 5 0 N/A 0 12 0 N/A 0 4 0 N/A 0 11 0 N/A 0 3 0 N/A 0 Description Device Global Enable 0 = ADC, DAC and PGA ramp control circuitry disabled 1 = ADC, DAC and PGA ramp control circuitry enabled 10 0 N/A 0 2 0 N/A 0 9 0 N/A 0 1 0 N/A 0
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8 0 N/A 0 0 GLOBAL_EN 0
N/A = Not Applicable (no function implemented)
Figure 36 R12 - Device Enable Register R13 (0Dh) - ADC Control Register 1 (ADC_CTRL1) Bit # Read Write Default Bit # Read Write Default Function ADC_FMT[1:0] ADC Audio Interface Format 00 = Right Justified 01 = Left Justified 10 = I2S 11 = DSP ADC Audio Interface Word Length 00 = 16-bit 01 = 20-bit 10 = 24-bit 11 = 32-bit (not available in Right Justified mode) ADC BCLK Polarity 0 = ADCBCLK not inverted - data latched on rising edge of BCLK 1 = ADCBCLK inverted - data latched on falling edge of BCLK ADC LRCLK Polarity 0 = ADCLRCLK not inverted 1 = ADCLRCLK inverted ADC Enable 0 = ADC disabled 1 = ADC enabled ADC Left/Right Swap 0 = Normal 1 = Swap left channel data into right channel and vice-versa 15 0 N/A 0 7 ADC_ LRSWAP 0 14 0 N/A 0 6 ADC_EN 0 13 ADC_ZCEN 1 5 ADC_LRP 0 12 ADC_HPD 0 4 ADC_BCP 0 11 10 9 ADCL_INV 0 1 8 ADCR_INV 0 0
ADC_DATA_SEL[1:0] 0 3 ADC_WL[1:0] 1 Description 0 0 2
ADC_FMT[1:0] 1 0
N/A = Not Applicable (no function implemented)
ADC_WL[1:0]
ADC_BCP
ADC_LRP
ADC_EN
ADC_LRSWAP
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WM8593
ADCL and ADCR Output Signal Inversion 0 = Output not inverted 1 = Output inverted ADC Data Output Select 00 = left data from ADCL, right data from ADCR (Normal Stereo) 01 = left data from ADCL, right data from ADCL (Mono Left) 10 = left data from ADCR, right data from ADCR (Mono Right) 11 = left data from ADCR, right data from ADCL (Reverse Stereo) ADC High Pass Filter Disable 0 = High pass filter enabled 1 = High pass filter disabled ADC Digital Volume Control Zero Cross Enable 0 = Do not use zero cross, change volume instantly 1 = Use zero cross, change volume when data crosses zero
ADCR_INV ADCL_INV ADC_DATA_SEL[1:0]
ADC_HPD
ADC_ZC_EN
Figure 37 R13 - ADC Control Register 1 R14 (0Eh) - ADC Control Register 2 (ADC_CTRL2) Bit # Read Write Default Bit # Read Write Default Function ADC_SR[2:0] ADC MCLK:LRCLK Ratio 000 = Auto detect 001 = reserved 010 = reserved 011 = 256fs 100 = 384fs 101 = 512fs 110 = 768fs 111 = Reserved ADC BCLK Rate (when ADC in Master Mode) 000 = MCLK / 4 001 = MCLK / 8 010 = 32fs 011 = 64fs 100 = 128fs All other values of ADC_BCLKDIV[2:0] are reserved 15 0 N/A 0 7 0 N/A 0 14 0 N/A 0 6 0 N/A 0 0 13 0 N/A 0 5 12 0 N/A 0 4 ADC_BCLKDIV[2:0] 0 0 Description 0 11 0 N/A 0 3 10 0 N/A 0 2 9 0 N/A 0 1 ADC_SR[2:0] 0 0 8 0 N/A 0 0
N/A = Not Applicable (no function implemented)
ADC_BCLKDIV[2:0]
Figure 38 R14 - ADC Control Register 2
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R15 (0Fh) - ADC Control Register 3 (ADC_CTRL3) Bit # Read Write Default Bit # Read Write Default Function ADC_MSTR 15 0 N/A 0 7 0 N/A 0 14 0 N/A 0 6 0 N/A 0 13 0 N/A 0 5 0 N/A 0 12 0 N/A 0 4 0 N/A 0 11 0 N/A 0 3 0 N/A 0 Description ADC Master Mode Select 0 = Slave mode, ADCBCLK and ADCLRCLK are inputs to WM8593 1 = Master mode, ADCBCLK and ADCLRCLK are outputs from WM8593 10 0 N/A 0 2 0 N/A 0 9 0 N/A 0 1 0 N/A 0
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8 0 N/A 0 0 ADC_MSTR 0
N/A = Not Applicable (no function implemented)
Figure 39 R15 - ADC Control Register 3 R16 (10h) - Left ADC Digital Volume Control Register (ADCL_VOL) Bit # Read Write Default Bit # Read Write Default Function ADCL_VOL[7:0] Left ADC Digital Volume 0000 0000 = Digital mute 0000 0001 = -97dB 0000 0010 = -96.5dB ...0.5dB steps 1100 0011 = 0dB ...0.5dB steps 1111 1110 = +29.5dB 1111 1111 = +30dB Left DAC Digital Volume Update 0 = Latch ADCL_VOL[7:0] into Register Map but do not update volume 1 = Latch ADCL_VOL[7:0] into Register Map and update left and right channels simultaneously 1 1 0 15 0 N/A 0 7 14 0 N/A 0 6 13 0 N/A 0 5 12 0 N/A 0 4 11 0 N/A 0 3 10 0 N/A 0 2 9 0 N/A 0 1 8 ADCL_VU 0 0
ADCL_VOL[7:0] 0 0 Description 0 1 1
N/A = Not Applicable (no function implemented)
ADCL_VU
Figure 40 R16 - Left ADC Digital Volume Control Register
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WM8593
R17 (11h) - Right ADC Digital Volume Control Register (ADCR_VOL) Bit # Read Write Default Bit # Read Write Default Function ADCR_VOL[7:0] Right ADC Digital Volume 0000 0000 = Digital mute 0000 0001 = -97dB 0000 0010 = -96.5dB ...0.5dB steps 1100 0011 = 0dB ...0.5dB steps 1111 1110 = +29.5dB 1111 1111 = +30dB Right ADC Digital Volume Update 0 = Latch ADCR_VOL[7:0] into Register Map but do not update volume 1 = Latch ADCR_VOL[7:0] into Register Map and update left and right channels simultaneously 1 1 0 15 0 N/A 0 7 14 0 N/A 0 6 13 0 N/A 0 5 12 0 N/A 0 4 11 0 N/A 0 3 10 0 N/A 0 2 9 0 N/A 0 1 8 ADCR_VU 0 0
ADCR_VOL[7:0] 0 0 Description 0 1 1
N/A = Not Applicable (no function implemented)
ADCR_VU
Figure 41 R17 - Right ADC Digital Volume Control Register
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R19 (13h) - PGA1L Volume Control Register (PGA1L_VOL) Bit # Read Write Default Bit # Read Write Default 0 0 0 15 0 N/A 0 7 14 0 N/A 0 6 13 0 N/A 0 5 12 0 N/A 0 4 11 0 N/A 0 3 10 0 N/A 0 2 9 0 N/A 0 1
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8 0 PGA1L_VU 0 0
PGA1L_VOL[7:0] 0 1 1 0 0
N/A = Not Applicable (no function implemented) R20 (14h) - PGA1R Volume Control Register (PGA1R_VOL) Bit # Read Write Default Bit # Read Write Default 0 0 0 15 0 N/A 0 7 14 0 N/A 0 6 13 0 N/A 0 5 12 0 N/A 0 4 11 0 N/A 0 3 10 0 N/A 0 2 9 0 N/A 0 1 8 0 PGA1R_VU 0 0
PGA1R_VOL[7:0] 0 1 1 0 0
N/A = Not Applicable (no function implemented) R21 (15h) - PGA2L Volume Control Register (PGA2L_VOL) Bit # Read Write Default Bit # Read Write Default 0 0 0 15 0 N/A 0 7 14 0 N/A 0 6 13 0 N/A 0 5 12 0 N/A 0 4 11 0 N/A 0 3 10 0 N/A 0 2 9 0 N/A 0 1 8 0 PGA2L_VU 0 0
PGA2L_VOL[7:0] 0 1 1 0 0
N/A = Not Applicable (no function implemented) R22 (16h) - PGA2R Volume Control Register (PGA2R_VOL) Bit # Read Write Default Bit # Read Write Default 0 0 0 15 0 N/A 0 7 14 0 N/A 0 6 13 0 N/A 0 5 12 0 N/A 0 4 11 0 N/A 0 3 10 0 N/A 0 2 9 0 N/A 0 1 8 0 PGA2R_VU 0 0
PGA2R_VOL[7:0] 0 1 1 0 0
N/A = Not Applicable (no function implemented) ...Continued on next page
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WM8593
R23 (17h) - PGA3L Volume Control Register (PGA3L_VOL) Bit # Read Write Default Bit # Read Write Default 0 0 0 15 0 N/A 0 7 14 0 N/A 0 6 13 0 N/A 0 5 12 0 N/A 0 4 11 0 N/A 0 3 10 0 N/A 0 2 9 0 N/A 0 1 8 0 PGA3L_VU 0 0
PGA3L_VOL[7:0] 0 1 1 0 0
N/A = Not Applicable (no function implemented) R24 (18h) - PGA3R Volume Control Register (PGA3R_VOL) Bit # Read Write Default Bit # Read Write Default 0 0 0 15 0 N/A 0 7 14 0 N/A 0 6 13 0 N/A 0 5 12 0 N/A 0 4 11 0 N/A 0 3 10 0 N/A 0 2 9 0 N/A 0 1 8 0 PGA3R_VU 0 0
PGA3R_VOL[7:0] 0 1 1 0 0
N/A = Not Applicable (no function implemented) PGA1L_VOL[7:0] PGA1R_VOL[7:0] PGA2L_VOL[7:0] PGA2R_VOL[7:0] PGA3L_VOL[7:0] PGA3R_VOL[7:0] Input PGA Volume 0000 0000 = +6dB 0000 0001 = +5.5dB ...0.5dB steps 00001100 = 0dB ... 1001 1110 = -73.5dB 1001 1111 = PGA Mute Input PGA Volume Update 0 = Latch corresponding volume setting into Register Map but do not update volume 1 = Latch corresponding volume setting into Register Map and update all channels simultaneously
PGA1L_VU PGA1R_VU PGA2L_VU PGA2R_VU PGA3L_VU PGA3R_VU
Figure 42 R19-24 - PGA Volume Control Registers
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R25 (19h) - PGA Control Register 1 (PGA_CTRL1) Bit # Read Write Default Bit # Read Write Default Function DECAY_BYPASS PGA Gain Decay Mode 0 = PGA gain will ramp down 1 = PGA gain will step down PGA Gain Attack Mode 0 = PGA gain will ramp up 1 = PGA gain will step up PGA Gain Zero Cross Enable 0 = PGA gain updates occur immediately 1 = PGA gain updates occur on zero cross Zero cross must be disabled to use gain ramp 15 0 N/A 0 7 PGA3R_ZC 1 14 0 N/A 0 6 PGA3L_ZC 1 13 0 N/A 0 5 PGA2R_ZC 1 12 0 N/A 0 4 PGA2L_ZC 1 11 0 N/A 0 3 PGA1R_ZC 1 Description 10 0 N/A 0 2 PGA1L_ZC 1 9 0 N/A 0 1 ATTACK_ BYPASS 0
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8 0 N/A 0 0 DECAY_ BYPASS 0
N/A = Not Applicable (no function implemented)
ATTACK_BYPASS
PGA1L_ZC PGA1R_ZC PGA2L_ZC PGA2R_ZC PGA3L_ZC PGA3R_ZC
Figure 43 R25 - PGA Control Register 1
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WM8593
R26 (1Ah) - PGA Control Register 2 (PGA_CTRL2) Bit # Read Write Default Bit # Read Write Default Function MUTE_ALL Master Output Driver Mute Control 0 = Unmute all output drivers 1 = Mute all output drivers Individual Output Drivers Mute Control 0 = Unmute output driver 1 = Mute output driver 15 0 N/A 0 7 JD_PGA1L_ MUTE 0 14 0 N/A 0 6 VOUT3R_ MUTE 1 13 0 N/A 0 5 VOUT3L_ MUTE 1 12 JD_PGA3R_ MUTE 0 4 VOUT2R_ MUTE 1 11 JD_PGA3L_ MUTE 0 3 VOUT2L_ MUTE 1 Description 10 JD_PGA2R_ MUTE 0 2 VOUT1R_ MUTE 1 9 JD_PGA2L_ MUTE 0 1 VOUT1L_ MUTE 1 8 JD_PGA1R_ MUTE 0 0 MUTE_ALL 0
N/A = Not Applicable (no function implemented)
VOUT1L_MUTE VOUT1R_MUTE VOUT2L_MUTE VOUT2R_MUTE VOUT3L_MUTE VOUT3R_MUTE JD_PGA1L_MUTE JD_PGA1R_MUTE JD_PGA2L_MUTE JD_PGA2R_MUTE JD_PGA3L_MUTE JD_PGA3R_MUTE
Jack Detect Mute Control 0 = Do not mute PGA when jack is detected 1 = Mute PGA when jack is detected
Figure 44 R26 - PGA Control Register 2
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R27 (1Bh) - Additional Control Register 1 (ADD_CTRL1) Bit # Read Write Default Bit # Read Write Default Function GPIO1_APP 15 0 N/A 0 7 0 N/A 0 1 14 0 N/A 0 6 13 0 N/A 0 5 PGA_SR[2:0] 0 0 12 0 N/A 0 4 11 0 N/A 0 3 AUTO_INC 1 Description GPIO1 Application Select 0 = Use GPIO1 as data pin for audio interface mux 1 = Use GPIO1 as input for jack detect GPIO2 Application Select 0 = Use GPIO2 as data pin for audio interface mux 1 = Use GPIO2 as input for jack detect Jack Detect Polarity 0 = Normal (active high) 1 = Inverted (active low) 2-wire Software Mode Auto Increment Enable 0 = Auto increment disabled 1 = Auto increment enabled Sample Rate for PGA 000 = 32kHz 001 = 44.1kHz 010 = 48kHz 011 = 88.2kHz 100 = 96kHz 101 = 176.4kHz 11X = 192kHz See Table 26 for further information on PGA sample rate versus volume ramp rate. 10 0 N/A 0 2 JD_INV 0 9 0 N/A 0 1 GPIO2_APP 0
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8 0 N/A 0 0 GPIO1_APP 0
N/A = Not Applicable (no function implemented)
GPIO2_APP
JD_INV
AUTO_INC
PGA_SR[2:0]
Figure 45 R27 - Additional Control Register 1
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WM8593
R28 (1Ch) - Input Control Register 1 (INPUT_CTRL1) Bit # Read Write Default Bit # Read Write Default 0 15 0 N/A 0 7 14 0 N/A 0 6 13 0 N/A 0 5 12 0 N/A 0 4 0 3 11 10 9 8
PGA2L_IN_SEL[3:0] 0 2 0 1 0 0
PGA1R_IN_SEL[3:0] 0 0 0 0
PGA1L_IN_SEL[3:0] 0 0 0
N/A = Not Applicable (no function implemented) R29 (1Dh) - Input Control Register 2 (INPUT_CTRL2) Bit # Read Write Default Bit # Read Write Default 0 15 0 N/A 0 7 14 0 N/A 0 6 13 0 N/A 0 5 12 0 N/A 0 4 0 3 11 10 9 8
PGA3R_IN_SEL[3:0] 0 2 0 1 0 0
PGA3L_IN_SEL[3:0] 0 0 0 0 Description Left Input PGA Source Selection 0000 = No input selected 0001 = VIN1L selected 0010 = VIN2L selected 0011 = VIN3L selected 0100 = VIN4L selected 0101 = VIN5L selected 0110 = VIN6L selected 0111 = VIN7L selected 1000 = VIN8L selected 1001 = DAC1L output selected 1010 = DAC1R output selected 1011 = DAC2L output selected 1100 = DAC2R output selected 1101 to 1111 = reserved Right Input PGA Source Selection 0000 = No input selected 0001 = VIN1R selected 0010 = VIN2R selected 0011 = VIN3R selected 0100 = VIN4R selected 0101 = VIN5R selected 0110 = VIN6R selected 0111 = VIN7R selected 1000 = VIN8R selected 1001 = DAC1L output selected 1010 = DAC1R output selected 1011 = DAC2L output selected 1100 = DAC2R output selected 1101 to 1111 = reserved
PGA2R_IN_SEL[3:0] 0 0 0
N/A = Not Applicable (no function implemented) Function PGA1L_IN_SEL[3:0] PGA2L_IN_SEL[3:0] PGA3L_IN_SEL[3:0]
PGA1R_IN_SEL[3:0] PGA2R_IN_SEL[3:0] PGA3R_IN_SEL[3:0]
Figure 46 R28-29 - Input Control Registers 1-2
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R30 (1Eh) - Input Control Register 3 (INPUT_CTRL3) Bit # Read Write Default Bit # Read Write Default Function ADCL_SEL[3:0] ADCR_SEL[3:0] ADC Input Select 0000 = VIN1L 0001 = VIN2L 0010 = VIN3L 0011 = VIN4L 0100 = VIN5L 0101 = VIN6L 0110 = VIN7L 0111 = VIN8L 1000 = VIN1R 1001 = VIN2R 1010 = VIN3R 1011 = VIN4R 1100 = VIN5R 1101 = VIN6R 1110 = VIN7R 1111 = VIN8R ADC Amplifier Gain Control 00 = 0dB 01 = +3dB 10 = +6dB 11 = +12dB ADC Input Switch Control 0 = ADC input switches open 1 = ADC input switches closed 1 15 0 N/A 0 7 14 0 N/A 0 6 13 0 N/A 0 5 12 0 N/A 0 4 11 0 N/A 0 3 10 ADC_ SWITCH_EN 0 2 9
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8
ADC_AMP_VOL[1:0] 1 1 0 0
ADCR_SEL[3:0] 0 0 0 0 Description
ADCL_SEL[3:0] 0 0 0
N/A = Not Applicable (no function implemented)
ADC_AMP_VOL[1:0]
ADC_SWITCH_EN
Figure 47 R30 - Input Control Register 3
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WM8593
R31 (1Fh) - Input Control Register 4 (INPUT_CTRL4) Bit # Read Write Default Bit # Read Write Default Function PGA1L_EN PGA1R_EN PGA2L_EN PGA2R_EN PGA3L_EN PGA3R_EN ADCL_AMP_EN ADCR_AMP_EN Input PGA Enable Controls 0 = PGA disabled 1 = PGA enabled 15 0 N/A 0 7 14 0 N/A 0 6 13 0 N/A 0 5 PGA3R_EN 0 12 0 N/A 0 4 PGA3L_EN 0 11 0 N/A 0 3 PGA2R_EN 0 Description 10 0 N/A 0 2 PGA2L_EN 0 9 0 N/A 0 1 PGA1R_EN 0 8 0 N/A 0 0 PGA1L_EN 0
ADCR_AMP_ ADCL_AMP_ EN EN 0 0
N/A = Not Applicable (no function implemented)
ADC Input Amplifier Enable Controls 0 = Amplifier disabled 1 = Amplifier enabled
Figure 48 R31 - Input Control Register 4
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R32 (20h) - Output Control Register 1 (OUTPUT_CTRL1) Bit # Read Write Default Bit # Read Write Default 15 0 N/A 0 7 14 0 N/A 0 6 13 0 N/A 0 5 12 0 N/A 0 4 VOUT1R _SEL[2:0] 0 0 1 0 11 0 N/A 0 3 10 0 N/A 0 2 9 0 N/A 0 1
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8 VOUT2L_ SEL[2] 0 0
VOUT2L_SEL[1:0] 1 0
VOUT1L_SEL[2:0] 0 0
N/A = Not Applicable (no function implemented) R33 (21h) - Output Control Register 2 (OUTPUT_CTRL2) Bit # Read Write Default Bit # Read Write Default Function VOUT1L_SEL[3:0] VOUT1R_SEL [3:0] VOUT2L_SEL [3:0] VOUT2R_SEL [3:0] VOUT3L_SEL [3:0] VOUT3R_SEL [3:0] Output Mux Selection 000 = PGA1L 001 = PGA1R 010 = PGA2L 011 = PGA2R 100 = PGA3L 101 = PGA3R 11X = Reserved 15 0 N/A 0 7 14 0 N/A 0 6 13 0 N/A 0 5 12 0 N/A 0 4 VOUT3L_SEL [2:0] 1 0 0 Description 0 11 0 N/A 0 3 10 0 N/A 0 2 9 0 N/A 0 1 VOUT2R_SEL[2:0] 1 1 8 VOUT3R_ SEL[2] 1 0
VOUT3R_SEL [1:0] 0 1
N/A = Not Applicable (no function implemented)
Figure 49 R32-33 - Output Control Registers 1-2
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WM8593
R34 (22h) - Output Control Register 3 (OUTPUT_CTRL3) Bit # Read Write Default Bit # Read Write Default Function VOUT1L_TRI VOUT1R_TRI VOUT2L_TRI VOUT2R_TRI VOUT3L_TRI VOUT3R_TRI APE_B Output Amplifier Tristate Control 0 = Normal operation 1 = Output amplifier tristate enable (Hi-Z) 15 0 N/A 0 7 VOUT1L_EN 0 14 0 N/A 0 6 APE_B 1 13 0 N/A 0 5 12 11 10 9 8
VOUT3R_EN VOUT3L_EN VOUT2R_EN VOUT2L_EN VOUT1R_EN 0 4 0 3 0 2 0 1 0 0
VOUT3R_TRI VOUT3L_TRI VOUT2R_TRI VOUT2L_TRI VOUT1R_TRI VOUT1L_TRI 0 0 0 Description 0 0 0
N/A = Not Applicable (no function implemented)
Clamp Outputs to Ground 0 = clamp active 1 = clamp not active Output Amplifier Enables 0 = Output amplifier disabled 1 = Output amplifier enabled
VOUT1L_EN VOUT1R_EN VOUT2L_EN VOUT2R_EN VOUT3L_EN VOUT3R_EN
Figure 50 R34 - Output Control Register 3
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R35 (23h) - Bias Control Register (BIAS) Bit # Read Write Default Bit # Read Write Default Function POBCTRL Bias Source for Output Amplifiers 0 = Output amplifiers use master bias 1 = Output amplifiers use fast bias VMID Power Down Characteristic 0 = Slow ramp 1 = Fast ramp Fast Bias Enable 0 = Fast bias disabled 1 = Fast bias enabled VMID Buffer Enable 0 = VMID Buffer disabled 1 = VMID Buffer enabled VMID Soft Ramp Enable 0 = Soft ramp disabled 1 = Soft ramp enabled Master Bias Enable 0 = Master bias disabled 1 = Master bias enabled Also powers down ADCVMID VMID Resistor String Value Selection (DACVMID only) 00 = off (no VMID) 01 = 100k 10 = 500k 11 = 10k The selection is the total resistance of the string from DACREFP to DACREFN. resistance is fixed at 200k. 15 0 N/A 0 7 14 0 N/A 0 6 13 0 N/A 0 5 BIAS_EN 0 12 0 N/A 0 4 SOFT_ST 1 11 0 N/A 0 3 BUFIO_EN 0 Description 10 0 N/A 0 2 FAST_EN 0 9 0 N/A 0 1 VMIDTOG 0
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8 0 N/A 0 0 POBCTRL 0
VMID_SEL[1:0] 0 0
N/A = Not Applicable (no function implemented)
VMIDTOG
FAST_EN
BUFIO_EN
SOFT_ST
BIAS_EN
VMID_SEL[1:0]
The ADCVMID
Figure 51 R35 - Bias Control Register
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WM8593
R36 (24h) - PGA Control Register 3 (PGA_CTRL3) Bit # Read Write Default Bit # Read Write Default Function PGA_FORCE 15 0 N/A 0 7 0 N/A 0 14 0 N/A 0 6 0 N/A 0 13 0 N/A 0 5 0 N/A 0 12 0 N/A 0 4 0 N/A 0 0 Description PGA Ramp Control Clock Source Mux Force Update 0 = Wait until clocks are safe before switching PGA clock source 1 = Force PGA clock source to change immediately See page 36 for details of use. PGA Ramp Control Clock Source 000 = LRCLK1 001 = LRCLK2 010 = LRCLK3 011 = LRCLK4 100 = LRCLK5 101 = DAC1LRCLK (when DAC1 is being used in master mode) 110 = DAC2LRCLK (when DAC2 is being used in master mode) 111 = ADCLRCLK (when ADC is being used in master mode) PGA Ramp Control Clock Source Mux Update 0 = Do not update PGA clock source 1 = Update clock source 11 0 N/A 0 3 10 PGA_UPD 0 2 PGA_SEL[2:0] 0 1 9 0 N/A 0 1 8 0 N/A 0 0 PGA_ FORCE 0
N/A = Not Applicable (no function implemented)
PGA_SEL[2:0]
PGA_UPD
Figure 52 R36 - PGA Control Register 3
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R37 (25h) - Audio Interface MUX Configuration Register 1 (AIF_MUX1) Bit # Read Write Default Bit # Read Write Default Function PORT1_FORCE 15 0 N/A 0 7 DIO1_ SEL[0] 0 0 14 0 N/A 0 6 13 0 N/A 0 5 WORDCLK1_SEL[2:0] 0 0 0 Description Force Port 1 Clocks to Change 0 = Wait until clocks are safe before switching between clock sources 1 = Force clock sources to change immediately See Table 40 for details of use. MCLK1 Pin Function Select 000 = Input to WM8593 001 = Output MCLK2 010 = Output MCLK3 011 = Output MCLK4 100 = Output MCLK5 101 to 111 = Reserved BCLK1 and LRCLK1 Pins Function Select 000 = Inputs to WM8593 001 = Source BCLK2 and LRCLK2 010 = Source BCLK3 and LRCLK3 011 = Source BCLK4 and LRCLK4 100 = Source BCLK5 and LRCLK5 101 = Source DAC1BCLK and DAC1LRCLK (when DAC1 is in master mode) 110 = Source DAC2BCLK and DAC2LRCLK (when DAC2 is in master mode) 111 = Source ADCBCLK and ADCBCLK (when ADC is master mode) DIO1 Pin Function Select 000 = Input to WM8593 001 = Source DIO2 010 = Source DIO3 011 = Source DIO4 100 = Source DIO5 101 = Source GPIO1 110 = Source GPIO2 111 = Source ADC Data Output Port 1 Update 0 = Latch corresponding Port 1 settings into Register Map but do not update 1 = Latch corresponding Port 1 settings into Register Map and update all simultaneously 12 0 N/A 0 4 11 0 N/A 0 3 10 PORT1_UPD 0 2 MCLK1_SEL[2:0] 0 0 9
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8
DIO1_SEL[2:1] 0 1 0 0 PORT1_ FORCE 0
N/A = Not Applicable (no function implemented)
MCLK1_SEL[2:0]
WORDCLK1_SEL[2:0]
DIO1_SEL[2:0]
PORT1_UPD
Figure 53 R37 - Audio Interface MUX Configuration Register 1
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WM8593
R38 (26h) - Audio Interface MUX Configuration Register 2 (AIF_MUX2) Bit # Read Write Default Bit # Read Write Default Function PORT2_FORCE 15 0 N/A 0 7 DIO2_ SEL[0] 1 0 14 0 N/A 0 6 13 0 N/A 0 5 WORDCLK2_SEL[2:0] 0 1 0 Description Force Port 2 Clocks to Change 0 = Wait until clocks are safe before switching between clock sources 1 = Force clock sources to change immediately See Table 40 for details of use. MCLK2 Pin Function Select 000 = Output MCLK1 001 = Input to WM8593 010 = Output MCLK3 011 = Output MCLK4 100 = Output MCLK5 101 to 111 = Reserved BCLK2 and LRCLK2 Pins Function Select 000 = Output BCLK1 and LRCLK1 001 = Inputs to WM8593 010 = Output BCLK3 and LRCLK3 011 = Output BCLK4 and LRCLK4 100 = Output BCLK5 and LRCLK5 101 = Output DAC1BCLK and DAC1LRCLK (when DAC1 is in master mode) 110 = Output DAC2BCLK and DAC2LRCLK (when DAC2 is in master mode) 111 = Output ADCBCLK and ADCBCLK (when ADC is master mode) DIO2 Pin Function Select 000 = Output DIO1 001 = Input to WM8593 010 = Output DIO3 011 = Output DIO4 100 = Output DIO5 101 = Output GPIO1 110 = Output GPIO2 111 = Output ADC Data Output Port 2 Update 0 = Latch corresponding Port 2 settings into Register Map but do not update 1 = Latch corresponding Port 2 settings into Register Map and update all simultaneously 12 0 N/A 0 4 11 0 N/A 0 3 10 PORT2_UPD 0 2 MCLK2_SEL[2:0] 0 1 9 8
DIO2_SEL[2:1] 0 1 0 0 PORT2_ FORCE 0
N/A = Not Applicable (no function implemented)
MCLK2_SEL[2:0]
WORDCLK2_SEL[2:0]
DIO2_SEL[2:0]
PORT2_UPD
Figure 54 R38 - Audio Interface MUX Configuration Register 2
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R39 (27h) - Audio Interface MUX Configuration Register 3 (AIF_MUX3) Bit # Read Write Default Bit # Read Write Default Function PORT3_FORCE 15 0 N/A 0 7 DIO3_ SEL[0] 0 0 14 0 N/A 0 6 13 0 N/A 0 5 WORDCLK3_SEL[2:0] 1 0 0 Description Force Port 3 Clocks to Change 0 = Wait until clocks are safe before switching between clock sources 1 = Force clock sources to change immediately See Table 40 for details of use. MCLK3 Pin Function Select 000 = Output MCLK1 001 = Output MCLK2 010 = Input to WM8593 011 = Output MCLK4 100 = Output MCLK5 101 to 111 = Reserved BCLK3 and LRCLK3 Pins Function Select 000 = Output BCLK1 and LRCLK1 001 = Output BCLK2 and LRCLK2 010 = Inputs to WM8593 011 = Output BCLK4 and LRCLK4 100 = Output BCLK5 and LRCLK5 101 = Output DAC1BCLK and DAC1LRCLK (when DAC1 is in master mode) 110 = Output DAC2BCLK and DAC2LRCLK (when DAC2 is in master mode) 111 = Output ADCBCLK and ADCBCLK (when ADC is master mode) DIO3 Pin Function Select 000 = Output DIO1 001 = Output DIO2 010 = Input to WM8593 011 = Output DIO4 100 = Output DIO5 101 = Output GPIO1 110 = Output GPIO2 111 = Output ADC Data Output Port 3 Update 0 = Latch corresponding Port 3 settings into Register Map but do not update 1 = Latch corresponding Port 3 settings into Register Map and update all simultaneously 12 0 N/A 0 4 11 0 N/A 0 3 10 PORT3_UPD 0 2 MCLK3_SEL[2:0] 1 0 9
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8
DIO3_SEL[2:1] 0 1 1 0 PORT3_ FORCE 0
N/A = Not Applicable (no function implemented)
MCLK3_SEL[2:0]
WORDCLK3_SEL[2:0]
DIO3_SEL[2:0]
PORT3_UPD
Figure 55 R39 - Audio Interface MUX Configuration Register 3
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WM8593
R40 (28h) - Audio Interface MUX Configuration Register 4 (AIF_MUX4) Bit # Read Write Default Bit # Read Write Default Function PORT4_FORCE 15 0 N/A 0 7 DIO4_ SEL[0] 1 0 14 0 N/A 0 6 13 0 N/A 0 5 WORDCLK4_SEL[2:0] 1 1 0 Description Force Port 4 Clocks to Change 0 = Wait until clocks are safe before switching between clock sources 1 = Force clock sources to change immediately See Table 40 for details of use. MCLK4 Pin Function Select 000 = Output MCLK1 001 = Output MCLK2 010 = Output MCLK3 011 = Input to WM8593 100 = Output MCLK5 101 to 111 = Reserved BCLK4 and LRCLK4 Pins Function Select 000 = Output BCLK1 and LRCLK1 001 = Output BCLK2 and LRCLK2 010 = Output BCLK3 and LRCLK3 011 = Inputs to WM8593 100 = Output BCLK5 and LRCLK5 101 = Output DAC1BCLK and DAC1LRCLK (when DAC1 is in master mode) 110 = Output DAC2BCLK and DAC2LRCLK (when DAC2 is in master mode) 111 = Output ADCBCLK and ADCBCLK (when ADC is master mode) DIO4 Pin Function Select 000 = Output DIO1 001 = Output DIO2 010 = Output DIO3 011 = Input to WM8593 100 = Output DIO5 101 = Output GPIO1 110 = Output GPIO2 111 = Output ADC Data Output Port 4 Update 0 = Latch corresponding Port 4 settings into Register Map but do not update 1 = Latch corresponding Port 4 settings into Register Map and update all simultaneously 12 0 N/A 0 4 11 0 N/A 0 3 10 PORT4_UPD 0 2 MCLK4_SEL[2:0] 1 1 9 8
DIO4_SEL[2:1] 0 1 1 0 PORT4_ FORCE 0
N/A = Not Applicable (no function implemented)
MCLK4_SEL[2:0]
WORDCLK4_SEL[2:0]
DIO4_SEL[2:0]
PORT4_UPD
Figure 56 R40 - Audio Interface MUX Configuration Register 4
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R41 (29h) - Audio Interface MUX Configuration Register 5 (AIF_MUX5) Bit # Read Write Default Bit # Read Write Default Function PORT5_FORCE 15 0 N/A 0 7 DIO5_ SEL[0] 0 1 14 0 N/A 0 6 13 0 N/A 0 5 WORDCLK5_SEL[2:0] 0 0 1 Description Force Port 5 Clocks to Change 0 = Wait until clocks are safe before switching between clock sources 1 = Force clock sources to change immediately See Table 40 for details of use. MCLK5 Pin Function Select 000 = Output MCLK1 001 = Output MCLK2 010 = Output MCLK3 011 = Output MCLK4 100 = Input to WM8593 101 to 111 = Reserved BCLK5 and LRCLK5 Pins Function Select 000 = Output BCLK1 and LRCLK1 001 = Output BCLK2 and LRCLK2 010 = Output BCLK3 and LRCLK3 011 = Output BCLK4 and LRCLK4 100 = Inputs to WM8593 101 = Output DAC1BCLK and DAC1LRCLK (when DAC1 is in master mode) 110 = Output DAC2BCLK and DAC2LRCLK (when DAC2 is in master mode) 111 = Output ADCBCLK and ADCBCLK (when ADC is master mode) DIO5 Pin Function Select 000 = Output DIO1 001 = Output DIO2 010 = Output DIO3 011 = Output DIO4 100 = Input to WM8593 101 = Output GPIO1 110 = Output GPIO2 111 = Output ADC Data Output Port 5 Update 0 = Latch corresponding Port 5 settings into Register Map but do not update 1 = Latch corresponding Port 5 settings into Register Map and update all simultaneously 12 0 N/A 0 4 11 0 N/A 0 3 10 PORT5_UPD 0 2 MCLK5_SEL[2:0] 0 0 9
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8
DIO5_SEL[2:1] 1 1 0 0 PORT5_ FORCE 0
N/A = Not Applicable (no function implemented)
MCLK5_SEL[2:0]
WORDCLK5_SEL[2:0]
DIO5_SEL[2:0]
PORT5_UPD
Figure 57 R41 - Audio Interface MUX Configuration Register 5
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WM8593
R42 (2Ah) - Audio Interface MUX Configuration Register 6 (AIF_MUX6) Bit # Read Write Default Bit # Read Write Default Function DAC1_FORCE 15 0 N/A 0 7 DAC1DIN_ SEL[0] 1 0 14 0 N/A 0 6 13 0 N/A 0 5 DAC1WORDCLK_SEL[2:0] 0 1 0 Description Force DAC1 Clocks to Change 0 = Wait until clocks are safe before switching between clock sources 1 = Force clock sources to change immediately See Table 40 for details of use. DAC1MCLK Select 000 = Use MCLK1 001 = Use MCLK2 010 = Use MCLK3 011 = Use MCLK4 100 = Use MCLK5 101 to 111 = Reserved DAC1BCLK and DAC1LRCLK Select 000 = Use BCLK1 and LRCLK1 001 = Use BCLK2 and LRCLK2 010 = Use BCLK3 and LRCLK3 011 = Use BCLK4 and LRCLK4 100 = Use BCLK5 and LRCLK5 101 = Output DAC1BCLK and DAC1LRCLK (when DAC1 is in master mode) 110 = Use DAC2BCLK and DAC2LRCLK (when DAC2 is in master mode) 111 = Use ADCBCLK and ADCBCLK (when ADC is master mode) DAC1DIN Select 000 = Use DIO1 001 = Use DIO2 010 = Use DIO3 011 = Use DIO4 100 = Use DIO5 101 = Use GPIO1 110 = Use GPIO2 111 = Use ADCDOUT DAC1 Clock Update 0 = Latch corresponding DAC1 clock settings into Register Map but do not update 1 = Latch corresponding DAC1 clock settings into Register Map and update all simultaneously 12 0 N/A 0 4 11 0 N/A 0 3 10 DAC1_UPD 0 2 DAC1MCLK_SEL[2:0] 0 1 9 8
DAC1DIN_SEL[2:1] 0 1 0 0 DAC1_ FORCE 0
N/A = Not Applicable (no function implemented)
DAC1MCLK_SEL[2:0]
DAC1WORDCLK_ SEL[2:0]
DAC1DIN_SEL[2:0]
DAC1_UPD
Figure 58 R42 - Audio Interface MUX Configuration Register 6
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R43 (2Bh) - Audio Interface MUX Configuration Register 7 (AIF_MUX7) Bit # Read Write Default Bit # Read Write Default Function DAC2_FORCE 15 0 N/A 0 7 DAC2DIN_ SEL[0] 1 0 14 0 N/A 0 6 13 0 N/A 0 5 DAC2WORDCLK_SEL[2:0] 0 1 0 Description Force DAC2 Clocks to Change 0 = Wait until clocks are safe before switching between clock sources 1 = Force clock sources to change immediately See Table 40 for details of use. DAC2MCLK Select 000 = Use MCLK1 001 = Use MCLK2 010 = Use MCLK3 011 = Use MCLK4 100 = Use MCLK5 101 to 111 = Reserved DAC2BCLK and DAC2LRCLK Select 000 = Use BCLK1 and LRCLK1 001 = Use BCLK2 and LRCLK2 010 = Use BCLK3 and LRCLK3 011 = Use BCLK4 and LRCLK4 100 = Use BCLK5 and LRCLK5 101 = Use DAC1BCLK and DAC1LRCLK (when DAC1 is in master mode) 110 = Output DAC2BCLK and DAC2LRCLK (when DAC2 is in master mode) 111 = Use ADCBCLK and ADCBCLK (when ADC is master mode) DAC2DIN Select 000 = Use DIO1 001 = Use DIO2 010 = Use DIO3 011 = Use DIO4 100 = Use DIO5 101 = Use GPIO1 110 = Use GPIO2 111 = Use ADCDOUT 12 0 N/A 0 4 11 0 N/A 0 3 10 DAC2_UPD 0 2 DAC2MCLK_SEL[2:0] 0 1 9
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8
DAC2DIN_SEL[2:1] 0 1 0 0 DAC2_ FORCE 0
N/A = Not Applicable (no function implemented)
DAC2MCLK_SEL[2:0]
DAC2WORDCLK_ SEL[2:0]
DAC2DIN_SEL[2:0]
DAC2_UPD
DAC2 Clock Update 0 = Latch corresponding DAC2 clock settings into Register Map but do not update 1 = Latch corresponding DAC2 clock settings into Register Map and update all simultaneously
Figure 59 R43 - Audio Interface MUX Configuration Register 7
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WM8593
R44 (2Ch) - Audio Interface MUX Configuration Register 8 (AIF_MUX8) Bit # Read Write Default Bit # Read Write Default Function ADC_FORCE 15 0 N/A 0 7 0 N/A 0 1 14 0 N/A 0 6 13 0 N/A 0 5 ADCWORDCLK_SEL[2:0] 0 0 1 Description Force ADC Clocks to Change 0 = Wait until clocks are safe before switching between clock sources 1 = Force clock sources to change immediately See Table 40 for details of use. ADCMCLK Select 000 = Use MCLK1 001 = Use MCLK2 010 = Use MCLK3 011 = Use MCLK4 100 = Use MCLK5 101 to 111 = Reserved ADCBCLK and ADCLRCLK Select 000 = Use BCLK1 and LRCLK1 001 = Use BCLK2 and LRCLK2 010 = Use BCLK3 and LRCLK3 011 = Use BCLK4 and LRCLK4 100 = Use BCLK5 and LRCLK5 101 = Use DAC1BCLK and DAC1LRCLK (when DAC1 is in master mode) 110 = Use DAC2BCLK and DAC2LRCLK (when DAC2 is in master mode) 111 = Output ADCBCLK and ADCBCLK (when ADC is master mode) ADC Clock Update 0 = Latch corresponding ADC clock settings into Register Map but do not update 1 = Latch corresponding ADC clock settings into Register Map and update all simultaneously 12 0 N/A 0 4 11 0 N/A 0 3 10 ADC_UPD 0 2 ADCMCLK_SEL[2:0] 0 0 9 0 N/A 1 1 8 0 N/A 0 0 ADC_ FORCE 0
N/A = Not Applicable (no function implemented)
ADCMCLK_SEL[2:0]
ADCWORDCLK_ SEL[2:0]
ADC_UPD
Figure 60 R44 - Audio Interface MUX Configuration Register 8
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R45 (2Dh) - Audio Interface MUX Configuration Register 9 (AIF_MUX9) Bit # Read Write Default Bit # Read Write Default Function GPIO1_SEL[2:0] GPIO1 Pin Function Select 000 = Source DIO1 001 = Source DIO2 010 = Source DIO3 011 = Source DIO4 100 = Source DIO5 101 = Input to WM8593 110 = Source GPIO2 111 = Source ADC Data Output GPIO1 Update 0 = Latch corresponding GPIO1 settings into Register Map but do not update 1 = Latch corresponding GPIO1 settings into Register Map and update 15 0 N/A 0 7 0 N/A 0 14 0 N/A 0 6 0 N/A 0 13 0 N/A 0 5 0 N/A 0 12 0 N/A 0 4 0 N/A 0 0 Description 11 0 N/A 0 3 10 GPIO1_UPD 0 2 GPIO1_SEL[2:0] 0 0 9 0 N/A 0 1
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8 0 N/A 0 0 0 N/A 0
N/A = Not Applicable (no function implemented)
GPIO1_UPD
Figure 61 R45 - Audio Interface MUX Configuration Register 9 R46 (2Eh) - Audio Interface MUX Configuration Register 10 (AIF_MUX10) Bit # Read Write Default Bit # Read Write Default Function GPIO2_SEL[2:0] GPIO2 Pin Function Select 000 = Source DIO1 001 = Source DIO2 010 = Source DIO3 011 = Source DIO4 100 = Source DIO5 101 = Input to WM8593 110 = Source GPIO2 111 = Source ADC Data Output GPIO2 Update 0 = Latch corresponding GPIO2 settings into Register Map but do not update 1 = Latch corresponding GPIO2 settings into Register Map and update all simultaneously 15 0 N/A 0 7 0 N/A 0 14 0 N/A 0 6 0 N/A 0 13 0 N/A 0 5 0 N/A 0 12 0 N/A 0 4 0 N/A 0 0 Description 11 0 N/A 0 3 10 GPIO2_UPD 0 2 GPIO2_SEL[2:0] 0 0 9 0 N/A 0 1 8 0 N/A 0 0 0 N/A 0
N/A = Not Applicable (no function implemented)
GPIO2_UPD
Figure 62 R46 - Audio Interface MUX Configuration Register 10
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WM8593
DIGITAL FILTER CHARACTERISTICS
PARAMETER ADC Filter Passband Passband Ripple Stopband Stopband Attenuation Group Delay DAC Filter - 32kHz to 96kHz Passband Passband Ripple Stopband Stopband attenuation Group Delay DAC Filter - 176.4kHz to 192kHz Passband Passband Ripple Stopband Stopband attenuation Group Delay f > 0.546fs 0.753fs -50 10 dB Fs 0.1dB 0.247fs 0.1 dB f > 0.546fs 0.546fs -50 10 dB Fs 0.1dB 0.454fs 0.1 dB 0.546fs -60 16 dB fs 0.05dB 0.454fs 0.05 dB TEST CONDITIONS MIN TYP MAX UNIT
DAC FILTER RESPONSES
0
0.2 0.15
-20
0.1 Response (dB) 0.05 0 -0.05 -0.1 -0.15
Response (dB)
-40
-60
-80
-100
-0.2 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Frequency (Fs)
0 0.5 1 1.5 Frequency (Fs) 2 2.5 3
-120
Figure 63 DAC Digital Filter Frequency Response - 44.1, 48 and 96KHz
Figure 64 DAC Digital Filter Ripple -44.1, 48 and 96kHz
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0.2
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0
0
-20 Response (dB)
Response (dB)
-0.2
-40
-0.4
-60
-0.6
-0.8
-80
-1
-100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (Fs)
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency (Fs)
Figure 65 DAC Digital Filter Frequency Response - 192KHz
Figure 66 DAC Digital Filter Ripple - 192kHz
DIGITAL DE-EMPHASIS CHARACTERISTICS
Figure 67 De-Emphasis Frequency Response (44.1KHz)
Figure 68 De-Emphasis Error (44.1KHz)
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WM8593
ADC FILTER RESPONSES
Magnitude (dB) up to fs 20 0 0.00 -20 -40 -60 -80 -100 -120 -140 Frequency
0.1 0.08 Magnitude (dB): Passband Ripple
0.25
0.50
0.75
0.06 0.04 0.02 0 0.00 -0.02 -0.04 -0.06 -0.08 -0.1 Frequency
0.25
Figure 69 ADC Digital Filter Frequency Response
Figure 70 ADC Digital Filter Ripple
ADC HIGH PASS FILTER
The WM8593 has a selectable digital high pass filter to remove DC offsets. The filter response is characterised by the following polynomial.
H(z) =
1 - z-1 1 - 0.9995z-1
0
-2
-4
-6
-8
-10
-12
-14
-16
-18
-20 0 2 4 6 8 10 12 14 16 18 20
MA GNITUDE(dB)
Figure 71 ADC Highpass Filter Response
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WM8593 APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
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Notes: 1. AGND and DGND should ideally share a continuous ground plane. Where this is not possible, it is recommended that AGND and DGND are connected as close to the WM8593 as possible. Decoupling capacitors shown are very low-ESR, multilayer ceramic capacitors and should be placed as near to the WM8593 as possible. Equally good results may be obtained using 0.1F ceramic capacitors near to the WM8593, with a 10F electrolytic capacitor nearby.
2.
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WM8593
RECOMMENDED ANALOGUE LOW PASS FILTER

Figure 72 Recommended Analogue Low Pass Filter (shown for VOUT1L/R) Note: See WAN0176 for AC coupling capacitor selection information. An external single pole RC filter is recommended (see Figure 72) if the device is driving a wideband amplifier. Other filter architectures may provide equally good results.
EXTENDED INPUT IMPEDANCE CONFIGURATION
Figure 73 Extended Input Impedance Configuration Note: See WAN0176 for AC coupling capacitor selection information. The input impedance to the WM8593 is specified in the Electrical Characteristics section beginning on p8, and is fixed across gain setting and signal routing options. If this input impedance is not enough for the intended application, an alternative input configuration (Figure 73) is possible. This configuration increases the input impedance to the WM8593 by 10k, but reduces the overall gain in the ADC and Bypass paths by -6dB. In order to compensate for this reduction in gain, +6dB of gain should be set in the ADC Input PGA (by using ADC_AMP_VOL[1:0]) and in the bypass PGA (by using PGAxx_VOL[7:0]). Examples: * If a 2VRMS signal is applied to VIN1L and VIN1R and routed to VOUT1L and VOUT1R using PGA1L and PGA1R, then setting PGA1L_VOL[7:0] and PGA1R_VOL[7:0] =0x00 is necessary to see 2VRMS at VOUT1L and VOUT1R. If a 2VRMS signal is applied to VIN1L and VIN1R and routed to ADCL and ADCR, then setting ADC_AMP_VOL[1:0]=10 is necessary to see 0dBFS at the ADC outputs.
*
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EXAMPLE CONFIGURATION FOR JACK DETECT
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The WM8593 contains a jack detect function as described on page 54. In order to use this function, it is necessary to connect the required GPIO pin to the headphone connector to detect the insertion of the jack. Figure 74 shows a typical connection scheme:
Figure 74 Example Jack Detect Circuitry When a jack is not inserted, the mechanical switch in the 3.5mm jack socket is closed and a short between pin 11 and pin 3 is present. There is a potential divider between DVDD and GND formed by R1 and R3, and this causes the voltage level at GPIO1 to be: DVDD * [R3 / (R1 +R3)] = DVDD * [10 / (470 + 10)] = 0.02 * DVDD = logic 0 When a jack is inserted, the mechanical switch in the 3.5mm jack socket is opened and there is no longer a short between pin 11 and pin 3. The voltage level at GPIO1 is then pulled up to DVDD through R1 and is therefore logic 1. Therefore, the function of the circuit in Figure 74 is: JACK STATUS Not Inserted Inserted LOGIC LEVEL AT GPIO1 Logic 0 Logic 1
Table 45 Example Jack Detect Configuration Operation
RELEVANT APPLICATION NOTES
The following application notes, available from www.wolfsonmicro.com, may provide additional guidance for the use of the WM8593.
DEVICE PERFORMANCE:
WAN0129 - Decoupling and Layout Methodology for Wolfson DACs, ADCs and CODECs WAN0144 - Using Wolfson Audio DACs and CODECs with Noisy Supplies WAN0176 - AC Coupling Capacitor Selection
GENERAL:
WAN0108 - Moisture Sensitivity Classification and Plastic IC Packaging WAN0109 - ESD Damage in Integrated Circuits: Causes and Prevention WAN0158 - Lead-Free Solder Profiles for Lead-Free Components
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WM8593
PACKAGE DIMENSIONS
FT: 64 PIN TQFP (10 x 10 x 1.0 mm) DM027.B
b e
48 33
49
32
E1
E
64
17 GAUGE PLANE
1
16
D1 D c L L1 0.25
A A2
A1
-CSEATING PLANE
ccc
C
Symbols A A1 A2 b c D D1 E E1 e L L1 ccc REF:
Dimensions (mm) MIN NOM MAX --------1.20 0.05 ----0.15 1.00 1.05 0.95 0.27 0.17 0.22 0.09 ----0.20 12.00 BSC 10.00 BSC 12.00 BSC 10.00 BSC 0.50 BSC 0.45 0.60 0.75 1.00 REF o o o 0 3.5 7 Tolerances of Form and Position 0.08 JEDEC.95, MS-026, VARIATION ACD
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MS-026, VARIATION = ACD. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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WM8593 IMPORTANT NOTICE
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Wolfson Microelectronics plc ("Wolfson") products and services are sold subject to Wolfson's terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson's products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer's own risk.
Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party's products or services does not constitute Wolfson's approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner.
Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon.
Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson's standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person's own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person.
ADDRESS
Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB
Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
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